9DB306BL

www.icst.com/products/hiperclocks.html

REV. A APRIL 7, 2005

1

Integrated

Circuit

Systems, Inc.

ICS9DB306

The ICS9DB306 is a high performance 1-to-6

Differential-to LVPECL Jitter Attenuator designed

for use in PCI Express™ systems. In some PCI

Express™ systems, such as those found in desktop

PCs, the PCI Express™ clocks are generated from

a low bandwidth, high phase noise PLL frequency

synthesizer. In these systems, a zero delay buffer may be

required to attenuate high frequency random and deterministic

jitter components from the PLL synthesizer and from the system

board. The ICS9DB306 has 2 PLL bandwidth modes. In low

bandwidth mode, the PLL loop BW is about 500kHz and this

setting will attenuate much of the jitter from the reference clock

input while being high enough to pass a triangular input spread

spectrum profile. There is also a high bandwidth mode which

sets the PLL bandwidth at 1MHz which will pass more spread

spectrum modulation.

For serdes which have x30 reference multipliers instead of x25

multipliers, 5 of the 6 PCI Express™ outputs (PCIEX1:5) can be

set for 125MHz instead of 100MHz by configuring the appropri-

ate frequency select pins (FS0:1). Output PCIEX0 will always

run at the reference clock frequency (usually 100MHz) in desk-

top PC PCI Express™ Applications.

Features

• Six differential LVPECL output pairs

• 1 differential clock input

• CLK and nCLK supports the following input types:

LVPECL, LVDS, LVHSTL, SSTL, HCSL

• Maximum output frequency: 140MHz

• Output skew: 135ps (maximum)

• Cycle-to-Cycle jitter: 25ps (maximum)

• RMS phase jitter @ 100MHz, (1.5MHz - 22MHz):

3ps (typical)

• 3.3V operating supply

• 0°C to 70°C ambient operating temperature

• Lead-Free package fully RoHS compliant

• Industrial temperature information available upon request

HiPerClockS™

ICS

nOE0

CLK

nCLK

BYPASS

nOE1

PCIEXT0

nPCIEXC0

PCIEXT1

nPCIEXC1

PCIEXT2

nPCIEXC2

PCIEXT3

nPCIEXC3

PCIEXT4

nPCIEXC4

PCIEXT5

nPCIEXC5

ICS9DB306

28-Lead TSSOP, 173-MIL

4.4mm x 9.7mm x 0.92mm

body package

L Package

Top View

PCIEXT1

PCIEXC1

PCIEXT2

PCIEXC2

nOE0

nOE1

PCIEXC3

PCIEXT3

PCIEXC4

PCIEXT4

PCIEXC0

PCIEXT0

FS0

nCLK

CLK

PLL_BW

BYPASS

FS1

PCIEXT5

PCIEXC5

ICS9DB306

28-Lead, 209-MIL SSOP

5.3mm x 10.2mm x 1.75mm

body package

F Package

Top View

Phase

Detector

VCO

Loop

Filter

1 Disabled

0 Enabled

1 Disabled

0 Enabled

÷5

0 ÷4

1 ÷5

0 ÷5

1 ÷4

FS0

FS1

Internal Feedback

÷5

0

1

0

1

0

1

Buffer

1

2

3

4

5

6

7

8

9

10

11

12

13

14

28

27

26

25

24

23

22

21

20

19

18

17

16

15