9DB306BL

www.icst.com/products/hiperclocks.html

REV. A APRIL 7, 2005

10

Integrated

Circuit

Systems, Inc.

ICS9DB306

Figure 5 shows an example of ICS9DB306 application

schematic. In this example, the device is operated at V

The decoupling capacitor should be located as close as pos-

sible to the power pin. The input is driven by a HCSL driver. For

LVPECL output drivers, one of terminations approaches is shown

in this schematic. For additional termination approaches, please

refer to the LVPECL Termination Application Note.

C3

0.1uF

C1

0.1uF

(U1-6)

VCC

R14

50

R15

50

Zo = 50

LVPECL

+

-

VCC=3.3V

(U1-15)

R13

33

R8

1K

VCC

R9

1K

U1

ICS9DB306

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

28

27

26

25

VEE

PCIEXT1

PCIEXC1

PCIEXT2

PCIEXC2

VCC

nOE0

nOE1

VCC

PCIEXC3

PCIEXT3

PCIEXC4

PCIEXT4

VEE

VCC

PCIEXC5

PCIEXT5

FS1

BY PASS

VEE

VCCA

PLL_BW

CLK

nCLK

VCC

PCIEXC0

PCIEXT0

FS0

HCSL

C3

0.1uF

VCCA

C11

0.1uF

Zo = 50

R16

50

(U1-9)

C2

0.1uF

R1

50

R11

1K

Zo = 50

C16

10uF

VCC

Zo = 50

VCC

R12

33

Zo = 50

R7

24

R10

1K

R6

50

R2

50

LVPECL

+

-

VCC

VCC

R5

50

R4

50

Zo = 50

(U1-28)