CY23FS08
Document #: 38-07518 Rev. *A
Page 9 of 12
Table 4. Operating Conditions for FailSafe Commercial/Industrial Temperature Devices
Parameter
Description
Min. Max. Unit
VDDC
3.3V Supply Voltage
3.135 3.465
V
VDDA,
VDDB
2.5V Supply Voltage Range
2.375 2.625
V
3.3V Supply Voltage Range
3.135 3.465
V
TA
Ambient Operating Temperature, Commercial
0
70
°C
Ambient Operating Temperature, Industrial
–40
85
°C
CL
Output Load Capacitance (Fout < 100 MHz)
30
pF
Output Load Capacitance (Fout > 100 MHz)
15
pF
CIN
Input Capacitance (except XIN)
7pF
CXIN
Crystal Input Capacitance (all internal caps off)
10
13
pF
TPU
Power-up time for all VDDs to reach minimum specified voltage (power ramps must be monotonic) 0.05
500
ms
Table 5. Electrical Characteristics for FailSafe Commercial/Industrial Temperature Devices
Parameter
Description
Test Conditions
Min.
Typ.
Max.
Unit
VIL
Input Low Voltage
CMOS Levels, 30% of VDD
0.3xVDD
V
VIH
Input High Voltage
CMOS Levels, 70% of VDD
0.7xVDD
V
IIL
Input Low Current
VIN=VSS (100k pull-up only)
50
µA
IIH
Input High Current
VIN=VDD (100k pull-down only)
50
µA
IOL
Output Low Current
VOL=0.5V, VDD= 2.5V
18
mA
VOL=0.5V, VDD= 3.3V
20
mA
IOH
Output High Current
VOH=VDD–0.5V, VDD= 2.5V
18
mA
VOH=VDD–0.5V, VDD = 3.3V
20
mA
IDDQ
Quiescent Current
All Inputs grounded, PLL and DCXO in
bypass mode, Reference Input = 0
250
µA
Table 6. Switching Characteristics for FailSafe Commercial/Industrial Temperature Devices
Parameter[8]
Description
Test Conditions
Min.
Max.
Unit
fREF
Reference Frequency
Commercial Grade
1.04
200
MHz
Industrial Grade
1.04
166.7
MHz
fOUT
Output Frequency
15-pF Load, Commercial Grade
1.70
200
MHz
15-pF Load, Industrial Grade
1.70
166.7
MHz
fXIN
DCXO Frequency
8.0
30
MHz
tDC
Duty Cycle
Measured at VDD/2
47
53
%
tSR(I)
Input Slew Rate
Measured on REF1 Input, 30% to 70% of VDD
0.5
4.0
V/ns
tSR(O)
Output Slew Rate
Measured from 20% to 80% of VDD = 3.3V, 15 pF Load
0.8
4.0
V/ns
Measured from 20% to 80% of VDD =2.5V, 15 pF Load
0.4
3.0
V/ns
tSK(O)
Output to Output Skew All outputs equally loaded, measured at VDD/2
200
ps
tSK(IB)
Intrabank Skew
All outputs equally loaded, measured at VDD/2
75
ps
tSK(PP)
Part to Part Skew
Measured at VDD/2
500
ps
t(φ)[7]
Static Phase Offset
Measured at VDD/2
250
ps
tD(φ)[7]
Dynamic Phase Offset Measured at VDD/2
200
ps
tJ(CC)
Cycle-to-Cycle Jitter
Load = 15 pF, fOUT ≥ 6.25 MHz
200
ps
35
psRMS
tLOCK
PLL Lock Time
Stable power supply, valid clock at REF
1.0
ms
Note:
7.
The
t(φ) reference feedback input delay is guaranteed for a maximum 4:1 input edge ratio between the two signals as long as tSR(I) is maintained.
8.
Parameters guaranteed by design and characterization, not 100% tested in production.
9.
Includes typical board trace capacitance of 6–7pF each XIN, XOUT.
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