CY23FS08
Document #: 38-07518 Rev. *A
Page 2 of 12
Pin Definitions
Pin Number
Pin Name
Description
1,2
REF1,REF2
5V-tolerant, reference clock inputs[4].
4,5,10,11
CLKB[1:4]
Bank B clock outputs.[1,2]
25,24,19,18
CLKA[1:4]
Bank A clock outputs.[1,2]
27
FBK
Feedback input to the PLL.[1,4]
23,6,7,22
S[1:4]
Frequency select pins/PLL and DCXO bypass.[3]
14
XIN
Reference crystal input.
15
XOUT
Reference crystal output.
16
FAIL#/SAFE
Valid reference indicator. A high level indicates a valid reference input.
13
VDDC
3.3V power supply for the internal circuitry.
8,12
VDDB
2.5V or 3.3V power supply for Bank B outputs.
3,9
VSSB
Ground.
17,21
VDDA
2.5V or 3.3V power supply for Bank A outputs.
20,26
VSSA
Ground.
28
REFSEL
Reference select. Selects the active reference clock from either REF1 or REF2.
REFSEL = 1, REF1 is selected, REFSEL = 0, REF2 is selected.
Table 1. Configuration Table
S[4:1]
XTAL (MHz)
REF(MHz)
OUT(MHz)
REF:OUT
ratio
REF:XTAL
ratio
Out:XTAL ratio
Min.
Max.
Min.
Max.
Min.
Max.
0000
PLL and DCXO Bypass mode
1000
8.33
30
16.67
60.00
8.33
30.00
÷22
1
1110
9.50
30
57.00
180.00
28.50
90.00
÷26
3
0101
8.50
30
6.80
24.00
1.70
6.00
÷44/5
1/5
1011
8.33
30
25.00
90.00
6.25
22.50
÷43
3/4
0011
8.33
30
2.78
10.00
2.78
10.00
x1
1/3
1/3
1001
8.33
30
8.33
30.00
8.33
30.00
x1
1
1
1111
8.00
25
32.00
100.00
32.00
100.00
x1
4
4
1100
8.00
25
64.00
200.00
64.00
200.00
x1
8
8
0001
8.33
30
1.04
3.75
2.08
7.50
x2
1/8
1/4
0110
8.33
30
4.17
15.00
8.33
30.00
x2
1/2
1
1101
8.33
30
16.67
60.00
33.33
120.00
x2
2
4
0100
8.33
30
4.17
15.00
16.67
60.00
x4
1/2
2
1010
8.33
30
12.50
45.00
50.00
180.00
x4
3/2
6
0010
8.33
30
1.39
5.00
11.11
40.00
x8
1/6
4/3
0111
8.33
30
6.25
22.50
50.00
180.00
x8
3/4
6
Notes:
1.
For normal operation, connect either one of the eight clock outputs to the FBK input.
2.
Weak pull-downs on all outputs.
3.
Weak pull-ups on these inputs.
4.
Weak pull-downs on these inputs.
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