8.3 Feature Description

8.3.1 Input and ESD Protection

The OPA855-Q1 is fabricated on a low-voltage, high-speed, BiCMOS process. The internal, junction breakdown

voltages are low for these small geometry devices, and as a result, all device pins are protected with internal

ESD protection diodes to the power supplies as Figure 8-3 shows. There are two antiparallel diodes between the

inputs of the amplifier that clamp the inputs during an overrange or fault condition.

+

±

VS+

VSí

VIN+

VOUT

Power Supply

ESD Cell

VINí

FB

Figure 8-3. Internal ESD Structure

8.3.2 Feedback Pin

The OPA855-Q1 pin layout is optimized to minimize parasitic inductance and capacitance, which is a critical care

about in high-speed analog design. The FB pin (pin 1) is internally connected to the output of the amplifier. The

FB pin is separated from the inverting input of the amplifier (pin 3) by a no connect (NC) pin (pin 2). The NC pin

must be left floating. There are two advantages to this pin layout:

Figure 8-4) rather than going around the package.

2. The isolation created by the NC pin minimizes the capacitive coupling between the FB and IN– pins by

increasing the physical separation between the pins.

1

FB

PD

8

2

NC

7

VS+

3

IN±

6

OUT

4

IN+

5

VS±

R

F

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OPA855-Q1

SBOSA57A – FEBRUARY 2021 – REVISED MARCH 2021

Copyright © 2021 Texas Instruments Incorporated

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Product Folder Links: OPA855-Q1