3

Integrated

Circuit

Systems, Inc.

ICS9DB102

0852C—09/12/05

The ICS9DB102 zero-delay buffer supports PCI Express clocking requirements. The ICS9DB102 is driven by a differential

SRC output pair from an ICS CK409/CK410-compliant main clock generator such as the ICS952601 or ICS954101. It

attenuates jitter on the input clock and has a selectable PLL Band Width to maximize performance in systems with or without

Spread-Spectrum clocking. An SMBus interface allows control of the PLL bandwidth and bypass options, while 2 clock

request (OE#) pins make the ICS9DB102 suitable for Express Card applications.

General Description

Block Diagram

Power Groups

SPREAD

COMPATIBLE

PLL

CONTROL

LOGIC

SMBDAT

SMBCLK

CLK_INT

C LK_IN C

PLL_BW

IREF

PCIEX0

PCIEX1

CLKREQ1#

CLKREQ0#

VDD

GND

5,9,12,16

6,15

PCI Express Outputs

96

SMBUS

20

19

IREF

20

19

Analog VDD & GND for PLL core

Description

Pin Number