Integrated

Circuit

Systems, Inc.

ICS9DB102

0852BC—09/12/05

Pin Configuration

Recommended Application:

•

1-to-2 Zero-delay or fanout buffer for PCI Express

Output Features:

•

2 - 0.7V current mode differential output pairs (HSCL)

Key Specifications:

•

Cycle-to-cycle jitter < 35ps

•

Output-to-output skew < 25 ps

Features/Benefits:

•

CLKREQ# pin for outputs 1 and 4/output enable for

Express Card applications

•

PLL or bypass mode/PLL can dejitter incoming clock

•

Selectable PLL bandwidth/minimizes jitter peaking in

downstream PLL’s

•

Spread Spectrum Compatible/tracks spreading input

clock for low EMI

•

SMBus Interface/unused outputs can be disabled

2 Output PCI Express* Buffer with CLKREQ# Function

20-pin SSOP & TSSOP

*Other names and brands may be claimed as the property of others.

PLL_BW 1

20 VDDA

CLK_INT 2

19 GNDA

CLK_INC 3

18 IREF

**CLKREQ0# 4

17 **CLKREQ1#

VDD 516 VDD

GND 6

15 GND

PCIEXT0 714 PCIEXT1

PCIEXC0 813 PCIEXC1

VDD 912 VDD

SMBDAT 10

11 SMBCLK

Note: Pins preceeded by '**' have internal

120K ohm pull down resistors