Advanced CMOS TTL Input – 74ACT574

Rev 1.0

19/3/2021

LIMITS

PARAMETER

SYMBOL

CONDITIONS

25°C

FULL RANGE

4

UNITS

85°C

4.5V

0.1

0.1

0.1

5.5V

0.1

0.1

0.1

V

4.5V

0.36

0.44

0.44

Maximum Low-Level

Output Voltage

5

0.36

0.44

5.5V

0.44

V

Maximum Input

Leakage Current

5.5V

±0.1

±1.0

±1.0

µA

Maximum 3-State

leakage current

5.5V

±0.5

±2.5

±2.5

µA

Additional Maximum

5.5V

1

1.5

1.5

mA

5.5V

-

75

75

Minimum Dynamic

Output Current

6

5.5V

mA

-

-75

-75

Maximum Quiescent

Supply Leakage

Current

5.5V

8

80

80

µA

5. All outputs loaded; thresholds on input associated with output under test. 6. Maximum test duration 2.0 ms, one output loaded at a time.

LIMITS

PARAMETER

SYMBOL

CONDITIONS

25°C

85°C

FULL RANGE

4

UNITS

Maximum Clock

Frequency

5V ±0.5

100

85

85

MHz

11

12

12

Propagation Delay

CLK to Q

(Figure 1,5)

5V ±0.5

ns

10

11

11

9.5

10

10

Output Enable Time

OE to Q

(Figure 3,6)

5V ±0.5

ns

9.0

10

10

10.5

11.5

11.5

Output Enable Time

OE to Q

ns

5V ±0.5

(Figure 3,6)

8.5

9.0

9.0

Maximum Input

Capacitance

5V ±0.5

10

10

10

pF

TYPICAL

Power Dissipation

pF

Capacitance

7

-

40

7. Not production tested in die form, characterized by chip design.

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