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VR4102 数据表(PDF) 51 Page - NEC |
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VR4102 数据表(HTML) 51 Page - NEC |
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51 / 701 page  CHAPTER 1 INTRODUCTION 51 1.5.6 Floating-Point Unit (FPU) The VR4102 does not support the floating-point unit (FPU). Coprocessor Unusable exception will occur if any FPU instructions are executed. If necessary, FPU instructions should be emulated by software in an exception handler. 1.5.7 Cache The VR4102 chip incorporates instruction and data caches, which are independent of each other. This configuration enables high-performance pipeline operations. Both caches have a 64-bit data bus, enabling a one- clock access. These buses can be accessed in parallel. The instruction cache of the VR4102 has a storage capacity of 4 KB, while the data cache has a capacity of 1 KB. A detailed description of caches is given in CHAPETE 8 CACHE ORGANIZATION AND OPERATION. |
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