VR4102 datasheet(13/701 Pages) NEC

13 / 701 page

CHAPTER 10 BCU (BUS CONTROL UNIT) ..................................................................................... 235

10.1 GENERAL................................................................................................................................ 235

10.2 REGISTER SET...................................................................................................................... 235

10.2.1 BCUCNTREG 1 (0x0B00 0000) ................................................................................................ 236

10.2.2 BCUCNTREG 2 (0x0B00 0002) ................................................................................................ 238

10.2.3 BCUSPEEDREG (0x0B00 000A) .............................................................................................. 239

10.2.4 BCUERRSTREG (0x0B00 000C) .............................................................................................. 241

10.2.5 BCURFCNTREG (0x0B00 000E) .............................................................................................. 242

10.2.6 REVIDREG (0x0B00 0010)........................................................................................................ 243

10.2.7 BCURFCOUNTREG (0x0B00 0012) ......................................................................................... 244

10.2.8 CLKSPEEDREG (0x0B00 0014) ............................................................................................... 245

10.3 CONNECTION OF ADDRESS PINS.................................................................................... 246

10.4 NOTES ON USING BCU ...................................................................................................... 247

10.4.1 CPU Core Bus Modes .............................................................................................................. 247

10.4.2 Access Data Size...................................................................................................................... 247

10.4.3 ROM Interface ........................................................................................................................... 248

10.4.4 Flash Memory Interface ........................................................................................................... 249

10.4.5 LCD Control Interface .............................................................................................................. 250

10.4.6 Illegal Access Notification....................................................................................................... 251

10.5 BUS OPERATIONS................................................................................................................ 252

10.5.1 ROM Access ............................................................................................................................. 252

10.5.2 System Bus Access ................................................................................................................. 256

10.5.3 LCD Interface ............................................................................................................................ 263

10.5.4 DRAM Access (EDO Type) ...................................................................................................... 264

10.5.5 Refresh...................................................................................................................................... 267

10.5.6 Bus Hold ................................................................................................................................... 268

CHAPTER 11 DMAAU (DMA ADDRESS UNIT)................................................................................ 271

11.1 GENERAL................................................................................................................................ 271

11.2 REGISTER SET...................................................................................................................... 272

11.2.1 AIU IN DMA Base Address Registers ..................................................................................... 273

11.2.2 AIU IN DMA Address Registers............................................................................................... 275

11.2.3 AIU OUT DMA Base Address Registers ................................................................................. 276

11.2.4 AIU OUT DMA Address Registers........................................................................................... 278

11.2.5 FIR DMA Base Address Registers .......................................................................................... 279

11.2.6 FIR DMA Address Registers.................................................................................................... 280

CHAPTER 12 DCU (DMA CONTROL UNIT) ..................................................................................... 281

12.1 GENERAL................................................................................................................................ 281

12.2 DMA PRIORITY CONTROL .................................................................................................. 281

12.3 REGISTER SET...................................................................................................................... 281

12.3.1 DMARSTREG (0x0B00 0040) ................................................................................................... 282

12.3.2 DMAIDLEREG (0x0B00 0042) .................................................................................................. 283

12.3.3 DMASENREG (0x0B00 0044) ................................................................................................... 284

12.3.4 DMAMSKREG (0x0B00 0046) .................................................................................................. 285

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