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ADRF5019BCPZN-R7 数据表(PDF) 10 Page - Analog Devices |
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ADRF5019BCPZN-R7 数据表(HTML) 10 Page - Analog Devices |
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10 / 12 page ![]() ADRF5019 Data Sheet Rev. 0 | Page 10 of 12 THEORY OF OPERATION The ADRF5019 integrates a driver to perform logic functions internally and to provide the user with the advantage of a simplified positive voltage control interface. The driver features two digital control input pins (VCTRL and LS) that control the state of the RF paths, determining which RF port is in the insertion loss state and which path is in the isolation state (see Table 5). RF INPUT AND OUTPUT The RF ports (RFC, RF1, and RF2) are dc-coupled to 0 V, and no dc blocking is required at the RF ports when the RF line potential is equal to 0 V. The RF ports are internally matched to 50 Ω. Therefore, external matching networks are not required. The ADRF5019 is bidirectional with equal power handling capabilities. An RF input signal (RFIN) can be applied to the RFC port or to the RF1 port or the RF2 port. The insertion loss path conducts the RF signal between the selected RF throw port and the RF common port. The isolation path provides high loss between the insertion loss path and the unselected RF throw port, which is nonreflective, by using an internal 50 Ω termination resistor. POWER SUPPLY The ADRF5019 requires a positive supply voltage applied to the VDD pin and a negative supply voltage applied to the VSS pin. Bypassing capacitors are recommended on the supply lines to filter high frequency noise. The ideal power-up sequence is as follows: 1. Connect to GND. 2. Power up the VDD and VSS voltages. Power up VSS after VDD to avoid current transients on VDD during ramp up. 3. Power up the digital control inputs. The order of the digital control inputs is not important. However, powering the digital control inputs before the VDD voltage supply can inadvertantly forward bias and damage the internal ESD protection structures. To avoid this damage, use a series 1 kΩ resistor to limit the current flowing into the control pin. Use pull-up or pull-down resistors if the controller output is in a high impedance state after the VDD voltage is powered up and the control pins are not driven to a valid logic state. 4. Apply an RF input signal to RFC, RF1, or RF2. The ideal power-down sequence is the reverse order of the power-up sequence. Single-Supply Operation The ADRF5019 can operate with a single positive supply voltage applied to the VDD pin and VSS pin connected to ground. However, some performance degradations can occur in the input compression and input third-order intercept. Table 5. Control Voltage Truth Table Digital Control Inputs RF Paths LS VCTRL RF1 to RFC RF2 to RFC High Low Insertion loss (on) Isolation (off) High High Isolation (off) Insertion loss (on) Low Low Isolation (off) Insertion loss (on) Low High Insertion loss (on) Isolation (off) |
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