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L6986ITR 数据表(PDF) 34 Page - STMicroelectronics |
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L6986ITR 数据表(HTML) 34 Page - STMicroelectronics |
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34 / 60 page  Figure 40. Slave-to-master mode transition The external master can force a latched SLAVE mode driving the SYNCH pin low at power-up, before the soft-start begins the switching activity. So the oscillator frequency is 250 kHz typ. fixed until a new UVLO event is triggered regardless FSW resistor value, that otherwise counts to design the slope compensation. The same considerations above are also valid. The master driving capability must be able to provide the proper signal levels at the SYNCH pin (see section 3): • Low level < VSYN THL = 0.7 V sinking 5 mA • High level > VSYN THH = 1.2 V sourcing 0.7 mA Figure 41. Master driving capability to synchronize the L6986I L6986I Synchronization DS13647 - Rev 1 page 34/60 |
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