ADRF6780ACPZN-R2 datasheet(21/35 Pages) AD

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Data Sheet

ADRF6780

Rev. D | Page 21 of 35

THEORY OF OPERATION

The ADRF6780 is a wideband microwave upconverter optimized

for point to point microwave radio designs operating in the

5.9 GHz to 23.6 GHz frequency range. A functional block

diagram of the device is shown in Figure 1. The ADRF6780 is

programmed via an SPI.

BASEBAND

The input impedance of the basebands are high input impedance.

These inputs are designed to operate with a 0.5 V common-

mode voltage. These inputs are differentially terminated to a

100 Ω resistor using an off chip termination.

The linearity can be optimized by adding phase correction

signals to the current output via adjusting the I_PATH_PHASE_

ACCURACY register (Register 0x05, Bits[3:0]) and the Q_PATH_

PHASE_ACCURACY (Register 0x05, Bits[7:4]) register.

SINGLE SIDEBAND (SSB) UPCONVERSION

The IF input path can be fed anywhere from 0.8 GHz to 3.5 GHz.

The IF inputs path can be upconverted to 5.9 GHz to 23.6 GHz,

while suppressing the unwanted sideband by typically better than

25 dBc. The IF upconversion inputs are 100 Ω differential and

must be ac-coupled. In addition, the I/Q baseband input must stay

floating without any termination on their inputs.

LO INPUT PATH

The LO input path operates from 5.4 GHz to 14 GHz with a LO

amplitude range of −6 dBm to +6 dBm. It is built from two modes:

×1 mode (Register 0x03, Bit 2), which provides an LO output

frequency equal to the LO input frequency, and ×2 mode

(Register 0x03, Bit 3), which doubles the LO output frequency

from the LO input frequency. Note that, when enabling the LO

×2 mode (Register 0x03, Bit 3), the LO ×1 mode (Register 0x03,

Bit 2) must be disabled.

The LO path is designed to operate differentially. LOIP and

LOIN are the inputs to the LO path. It is recommended to

use the ADRF6780 with a LO differential input to achieve the

best performance.

Figure 67 shows a block diagram of the LO path.

×2

PPF

MUX

PPF

AMP1

LOIP

LOIN

Figure 67. LO Path Block Diagram

SERIAL PORT INTERFACE (SPI)

The SPI of the ADRF6780 allows the user to configure the device

for specific functions or operations via a 4-pin SPI port. This

interface provides users with added flexibility and customization.

The SPI consists of four control lines: SCLK, SDIN, SDTO,

and SEN.

The ADRF6780 protocol consists of a write/read bit followed by

six register address bits, 16 data bits, and a parity bit. Both the

address and data fields are organized MSB first and end with the

least significant bit (LSB). For a write, set the first bit to 0, and

for a read, set this bit to 1.

The write cycle sampling must be done on the rising edge. The

16 bits of the serial write data are shifted in, MSB to LSB. The

ADRF6780 input logic level for the write cycle supports an 1.8 V

interface.

For a read cycle, up to 16 bits of serial read data are shifted out,

MSB first. After the 16 bits of data shift out, the parity bit shifts

out. The output logic level for a read cycle is 1.8 V.

The parity bit always follows the direction of the data. If parity

is not used, the transmitting end transmits zero instead of parity.

The parity is odd, which means that the total number of ones

transmitted during a command, including the read/write bit,

the address bit, the data bit, and the parity bit, must be odd.

Table 5. Serial Port Register Timing

Parameter

Description

Min

Typ

Max

Unit

tDI, SETUP

Data to clock setup time

tDI, HOLD

Data to clock hold time

tCLK, HIGH

Clock high duration

40 to 60

tCLK, LOW

Clock low duration

40 to 60

tCLK, SEN_SETUP

Clock to SEN setup time

tCLK, DOT

Clock to data out transition time

tCLK, DOV

Clock to data out valid time

tCLK, SEN_INACTIVE

Clock to SEN inactive

SEN_INACTIVE

Inactive SEN (between two operations)

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