| 数据搜索系统,热门电子元器件搜索 |
|
ADTR1107ACCZ-R7 数据表(PDF) 6 Page - Analog Devices |
|
|
|||||||||||||||||||||||||||||
ADTR1107ACCZ-R7 数据表(HTML) 6 Page - Analog Devices |
|
6 / 28 page ![]() ADTR1107 Data Sheet Rev. A | Page 6 of 28 ABSOLUTE MAXIMUM RATINGS Table 6. Parameter Rating Transmit State (PA On), Receive State Off VDD_PA 5.5 V VGG_PA −2 V to +0 V Continuous Wave (CW) RF Input Power (RFIN) at TX_IN 20 dBm Continuous Power Dissipation (PDISS) (TA = 85°C, Derate 18.98 mW/°C 1.71 W Above 85°C) Receive State (LNA On), Transmit State Off VDD_LNA 4 V VGG_LNA −2 V to +0.2 V CW RFIN at ANT 20 dBm PDISS (TA = 85°C, Derate 5.04 mW/°C Above 85°C) 0.453 W Transmit and Receive States Output Load Voltage Standing Wave Ratio (VSWR) 7:1 VDD_SW Range −0.3 V to +3.6 V VSS_SW Range −3.6 V to +0.3 V VDD_CTRL Range −0.3 V to VDD + 0.3 V Channel Temperature 175°C Maximum Peak Reflow Temperature (Moisture Sensitivity Level 3, MSL3)1 260°C Storage Temperature Range −40°C to +125°C Operating Temperature Range −40°C to +85°C ESD Sensitivity (Human Body Model) Class 1B (Passed ±500 V) 1 See the Ordering Guide section for more information. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. THERMAL RESISTANCE Thermal performance is directly linked to printed circuit board (PCB) design and operating environment. Careful attention to PCB thermal design is required. θJC is the thermal resistance from the operating portion of the device to the outside surface of the package (case) closest to the device mounting area. Table 7. Thermal Resistance1 Package Type θJC Transmit State θJC Receive State Unit CC-24-8 52.7 198.4 °C/W 1 Thermal impedance simulated values are based on a JEDEC 2S2P thermal test board with 36 thermal vias. Refer to the JEDEC standard JESD51 for additional information. ESD CAUTION Table 8. Signal Path Truth Table State CTRL_SW RF Signal Path Transmit Low TX_IN to ANT Receive High ANT to RX_OUT |
|
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |