6

Device description

The STSPIN32F060x is a system-in-package providing an integrated solution suitable for driving high-voltage

3-phase applications.

6.1

Gate driver

The STSPIN32F060x integrates a triple half-bridge gate driver able to drive N-channel power MOSFETs or IGBTs.

The high-side section is supplied by a bootstrapped voltage technique with integrated bootstrap diode.

All the inputs lines are connected to a pull-down resistor with typical value of 60 kΩ.

The high- and low-side outputs of same half-bridge cannot be simultaneously driven high thanks to an integrated

interlocking function.

6.1.1

Inputs and outputs

The device is controlled through the following logic inputs:

•

EN: enable input, active high;

•

LIN: low-side driver inputs, active low;

•

HIN: high-side driver inputs, active low.

Input pins

Output pins

EN

LIN

HIN

LVG

HVG

L

X

X

Low

Low

H

H

H

Low

Low

H

L

H

HIGH

Low

H

H

L

Low

HIGH

Interlocking

H

L

L

Low

Low

Note:

X : Don’t care

The FAULT and OD pins are open-drain outputs. The FAULT signal is set low in case VCC UVLO is detected, or

in case the SmartShutDown comparator triggers an event. It is only used to signal a UVLO or SmartSD activation

to external circuits, and its state does not affect the behavior of other functions or circuits inside the driver. The

OD behavior is explained in Section 6.1.5 .

6.1.2

Deadtime

The deadtime feature, in companion with the interlocking feature, guarantees that driver outputs of the same

channel are not high simultaneously and at least a DT time passes between the turn-off of one driver's output and

the turn-on of the companion output of the same channel. If a deadtime longer than the internal DT is applied

to LIN and HIN inputs by the external controller, the internal DT is ignored and the outputs follow the deadtime

determined by the inputs. Refer to Figure 4 for the deadtime and interlocking waveforms.

6.1.3

VCC UVLO protection

Undervoltage protection is available on VCC and BOOT supply pins. In order to avoid intermittent operation, a

hysteresis sets the turn-off threshold with respect to the turn-on threshold.

according to actual input pins status; HVG is also set according to input pin status if the corresponding VBO

section is not in UVLO condition. The FAULT output is kept low when VCC is in UVLO condition. The following

figures show some examples of typical operation conditions.

STSPIN32F0601, STSPIN32F0602

Device description

DS12981 - Rev 5

page 16/32