List of figures

Figure 1.

STSPIN32F060x SiP block diagram ..................................................... 3

Figure 2.

STSPIN32F060x pin connection (TQFP top view) ............................................ 4

Figure 3.

STSPIN32F060x pin connection (QFN top view) ............................................. 4

Figure 4.

Propagation delay timing definition ..................................................... 14

Figure 5.

Deadtime timing definitions .......................................................... 14

Figure 6.

Deadtime and interlocking waveforms definition ............................................ 15

Figure 7.

VCC power ON and UVLO, LVG timing .................................................. 17

Figure 8.

VCC power ON and UVLO, HVG timing .................................................. 17

Figure 9.

VBO Power-ON and UVLO timing ...................................................... 18

Figure 10.

Smart shutdown timing waveforms ..................................................... 19

Figure 11.

Typical application with 8 MHz crystal ................................................... 21

Figure 12.

HSE clock source timing diagram ...................................................... 21

Figure 13.

TQFP mechanical data ............................................................. 23

Figure 14.

QFN mechanical data .............................................................. 25

Figure 15.

TQFP 10x10 64L suggested land pattern ................................................. 26

Figure 16.

QFN 10x10 72L suggested land pattern .................................................. 26

STSPIN32F0601, STSPIN32F0602

List of figures

DS12981 - Rev 5

page 31/32