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MCP48CMB21 数据表(PDF) 72 Page - Microchip Technology

部件名 MCP48CMB21
功能描述  8/10/12-Bit Digital-to-Analog Converters, 1 LSb INL Single/Dual Voltage Outputs with SPI Interface
PDF  106 Pages
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制造商  MICROCHIP [Microchip Technology]
网页  http://www.microchip.com
标志 MICROCHIP - Microchip Technology

MCP48CMB21 数据表(HTML) 72 Page - Microchip Technology

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MCP48CXBXX
DS20006160A-page 72
 2019 Microchip Technology Inc.
7.5.3
CONTINUOUS WRITES TO
VOLATILE MEMORY
Continuous writes are possible only when writing to
the volatile memory registers.
Figure 7-3 shows the sequence for three continuous
writes. The writes do not need to be to the same
volatile memory address.
7.5.4
CONTINUOUS WRITES TO
NONVOLATILE MEMORY
Continuous writes to nonvolatile memory are not
allowed, and attempts to do so will result in a
command error (CMDERR) condition.
FIGURE 7-3:
Continuous Write Sequence (Volatile Memory Only).
12-bit data
10-bit data
8-bit data
SDI
AD
4
AD
3
AD
2
AD
1
AD
0
C
1
C
0
X
X
X
X
X
D
11
D
10
D
09
D
08
D
07
D
06
D
05
D
04
D
03
D
02
D
01
D
00
**
**
*
0
0
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
SDO
11
11
11
1
1
11
11
11
11
11
11
11
11 Valid(2)
11
11
11
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0 Invalid(3)
Note 1: For Write commands addressing the DAC Wiper Registers, the Data bits depend on the
resolution of the device: 12-bit = D11:D00, 10-bit = D09:D00, and 8-bit = D07:D00.
Data are right justified for easy Host Controller operation (no data manipulation before
transmitting the desired value). The unimplemented bits are ignored.
2: After a valid memory address and a Write command byte are received (CMDERR = ‘1’), all
the following SDO bits will be output as ‘1’.
3: If an Error Condition occurs (CMDERR = ‘0’), all the following SDO bits will be output as ‘0’
until the CMDERR condition is cleared (the CS pin is forced to the Inactive state).
4: This CMDERR bit will be forced to ‘0’, regardless if this Address + Command combination
is valid. This command will not be completed and requires the CS pin to return to VIH to clear
the CMDERR condition.
SDI
AD
4
AD
3
AD
2
AD
1
AD
0
C
1
C
0
X
X
X
X
X
D
11
D
10
D
09
D
08
D
07
D
06
D
05
D
04
D
03
D
02
D
01
D
00
**
**
*
0
0
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
SDO
11
11
11
1
1
11
11
11
11
11
11
11
11 Valid(2)
(3) 0
00
00
0 (4) 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0 Invalid(3)
SDI
AD
4
AD
3
AD
2
AD
1
AD
0
C
1
C
0
X
X
X
X
X
D
11
D
10
D
09
D
08
D
07
D
06
D
05
D
04
D
03
D
02
D
01
D
00
**
**
*
0
0
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
SDO
11
11
11
1
1
11
11
11
11
11
11
11
11 Valid(2)
(3) 0
00
00
0 (4) 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0 Invalid(3)
(1)
(1)
(1)



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