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MCP48CMB21 数据表(PDF) 76 Page - Microchip Technology |
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MCP48CMB21 数据表(HTML) 76 Page - Microchip Technology |
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76 / 106 page ![]() MCP48CXBXX DS20006160A-page 76 2019 Microchip Technology Inc. 8.1.2 LAYOUT CONSIDERATIONS Several layout considerations may be applicable to your application. These may include: • Noise • PCB Area Requirements 8.1.2.1 Noise Inductively-coupled AC transients and digital switching noise can degrade the input and output signal integrity, potentially masking the MCP48CXBXX’s performance. Careful board layout minimizes these effects and increases the Signal-to-Noise Ratio (SNR). Multilayer boards utilizing a low-inductance ground plane, isolated inputs, isolated outputs and proper decoupling are critical to achieving the performance that the silicon is capable of providing. Particularly harsh environments may require shielding of critical signals. Separate digital and analog ground planes are recommended. In this case, the VSS pin and the ground pins of the VDD capacitors must be terminated to the analog ground plane. 8.1.2.2 PCB Area Requirements In some applications, PCB area is a criteria for device selection. Table 8-1 shows the typical package dimensions and area for the different package options. Note: Breadboards and wire-wrapped boards are not recommended. TABLE 8-1: PACKAGE FOOTPRINT(1) Package Package Footprint Type Code Dimensions (mm) Area (mm2) Length Width 10 MSOP UN 3.00 4.90 14.70 10 DFN MF 3.00 3.00 9.00 16 QFN MG 3.00 3.00 9.00 Note 1: Does not include recommended land pattern dimensions. Dimensions are typical values. |
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