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MCP47FVB11 数据表(PDF) 3 Page - Microchip Technology |
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MCP47FVB11 数据表(HTML) 3 Page - Microchip Technology |
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3 / 92 page  2015 Microchip Technology Inc. DS20005429B-page 3 MCP48FEBXX MCP48FEBX2 Device Block Diagram (Dual-Channel Output) Power-up/ Brown-out Control VDD VSS SPI Serial Interface Module VREF LAT/HVC Op Amp Gain VOUT1 intVR1 PD1:PD0 and VREF1:VREF0 VREF1:VREF0 + - VDD PD1:PD0 and VREF1:VREF0 VREF1:VREF0 + - VDD SDI SDO Band Gap (1.22V) Band Gap (1.22V) PD1:PD0 VDD VBG VDD VSS VSS PD1:PD0 Op Amp Gain VOUT0 Memory (32x16) DAC0 and 1 (Vol & NV) VREF (Vol and NV) Power-down (Vol and NV) Gain (Vol and NV) Status (Vol) VREF1:VREF0 and PD1:PD0 VREF1:VREF0 and PD1:PD0 PD1:PD0 PD1:PD0 (1) (1) Note 1: If Internal Band Gap is selected, this buffer has a 2x gain, if the G bit = ‘1’, this is a total gain of 4. SCK CS and Control Logic (WiperLock™ Technology) |
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