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MCP47FVB02 数据表(PDF) 65 Page - Microchip Technology |
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MCP47FVB02 数据表(HTML) 65 Page - Microchip Technology |
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65 / 92 page ![]() 2015 Microchip Technology Inc. DS20005429B-page 65 MCP48FEBXX 7.3 Commands to Modify the Device Configuration Bits The MCP48FEBXX devices support two commands which are used to program the device’s configuration bits. These commands require a high voltage (VIHH) on the HVC pin. These commands are: • Enable Configuration Bit • Disable Configuration Bit The configuration bits are used to inhibit the DAC values from inadvertent modification. High voltage is required to change the state of these bits if/when the DAC values need to be modified. 7.4 Enable Configuration Bit (High Voltage) Figure 7-11 (Enable) shows the formats for a single Enable Configuration Bit command. The command will only start the EEPROM write cycle (tWC) after a properly formatted command has been received. During an EEPROM write cycle, only serial commands to volatile memory are accepted. All other serial commands are ignored until the EEPROM write cycle (tWC) completes. This allows the Host Controller to operate on the volatile DAC, the volatile VREF, Power-Down, Gain and Status, and WiperLock Technology Status registers. The EEWA bit in the Status register indicates the status of the EEPROM write cycle. 7.4.1 HIGH-VOLTAGE COMMAND (HVC) SIGNAL The High-Voltage Command (HVC) signal is used to indicate that the command, or sequence of commands, are in the High-Voltage mode. Signals higher than VIHH (~9.0V) on the LAT/HVC pin puts the device into High-Voltage mode. High-Voltage commands allow the device’s WiperLock technology and write-protect features to be enabled and disabled. FIGURE 7-11: Enable Command Sequence. Note 1: There is a required delay after the HVC pin is driven to the VIHH level on the 1st edge of the SCK pin. A D 4 A D 3 A D 2 A D 1 A D 0 10 C M D E R R A D 4 A D 3 A D 2 A D 1 A D 0 10 C M D E R R 1111111111111111 Valid 1111111 0 0 0 0 0 0 0 0 Invalid (1, 2) SDI SDO Note 1: If an Error condition occurs (CMDERR = L), all following SDO bits will be low until the CMDERR condition is cleared (the CS pin is forced to the inactive state). 2: This CMDERR bit will be forced to ‘0’, regardless if this Address+Command combination is valid. This command will not be completed and requires the CS pin to return to VIH to clear the CMDERR condition. Address Command |
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