HMC525ALC4TR-R5 datasheet(27/28 Pages) AD

27 / 28 page

Data Sheet

HMC525ALC4

Rev. A | Page 27 of 28

SOLDERING INFORMATION AND RECOMMENDED

LAND PATTERN

Figure 102 shows the recommended land pattern for the

HMC525ALC4. The HMC525ALC4 is contained in a 4 mm ×

4 mm, 24-terminal, ceramic LCC package, with an exposed

ground pad (EPAD). This pad is internally connected to the

ground of the chip. To minimize thermal impedance and ensure

electrical performance, solder the pad to the low impedance

ground plane on the PCB. It is recommended that the ground

planes on all layers under the pad be stitched together with vias,

to further reduce thermal impedance. The land pattern on the

EV1HMC525ALC4 evaluation board provides a simulated

thermal resistance (θJC) of 161°C/W.

.010" REF

.030"

MASK OPENING

.098" SQUARE MASK OPENING

.020 × 45" CHAMFER FOR PIN 1

.106" SQUARE

GROUND PAD

.116"

MASK

OPENING

PIN 1

.0197"

[0.50]

.034"

TYPICAL

VIA

SPACING

PAD SIZE

.026" × .010"

ᶲ .010"

TYPICAL VIA

GROUND PAD

SOLDERMASK

.004" MASK/METAL OVERLAP

.178" SQUARE

.010" MIN MASK WIDTH

Figure 102. Evaluation Board Land Pattern for the HMC525ALC4 Package

Figure 103. Evaluation PCB Top Layer

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