K32L2AX datasheet(12/96 Pages) NXP

12 / 96 page

The SCG module supplies peripheral interface and functional clocks to the PCC,

depending on the peripheral. The peripheral interface clock can be either the

DIVCORE_CLK or the DIVSLOW_CLK, depending on the peripheral. The peripheral

functional clocks and the peripheral interface clocks for each module/peripheral are

detailed in table below.

Table 4. Peripheral Clocks

Source Module

Module Reset

Bus Interface

Clock

Bus Interface

Clock Gating

Control

Peripheral

Functional Clock

PCCn Functional

Clock Divider

System

Coretex M0+ Core

controller

Chip Reset

DIVCORE_CLK

DMA controller

Chip Reset

DIVCORE_CLK

Yes

DMA channel

multiplexer

(DMAMUX)

Chip Reset

DIVSLOW_CLK

Yes

AXBS

Chip Reset

DIVCORE_CLK

AIPS

Chip Reset

DIVCORE_CLK

INTMUX

Chip Reset

DIVSLOW_CLK

LLWU

Chip Reset not

VLLS

DIVSLOW_CLK

LPO

SCG

Chip Reset

DIVSLOW_CLK

PCC

Chip Reset

DIVSLOW_CLK

PORT multiplex

control

Chip Reset

DIVSLOW_CLK

Yes

SIM

Chip Reset

DIVSLOW_CLK

Power

Management

Controller (PMC)

POR

DIVSLOW_CLK

System Mode

Controller (SMC)

Chip Reset not

VLLS

DIVSLOW_CLK

Reset Control

Module (RCM)

POR/LVD/VLLS

DIVSLOW_CLK

LPO

Security/Integrity

WDOG1

Chip Reset

DIVSLOW_CLK

LPO, ERCLK,

SIRC

TRNG

Chip Reset

DIVSLOW_CLK

Yes

CAU

Chip Reset

DIVCORE_CLK

CRC

Chip Reset

DIVSLOW_CLK

Yes

Memory

Flash Memory Unit Early Reset

DIVSLOW_CLK

Yes

Flash Memory

Controller

Chip Reset

DIVCORE_CLK

Table continues on the next page...

Overview

K32 L2A Microcontroller with 512 KB Flash and 128 KB SRAM, Rev. 3, 02/2021

NXP Semiconductors

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