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MCP3461RT-E/ST 数据表(PDF) 30 Page - Microchip Technology

部件名 MCP3461RT-E/ST
功能描述  Two/Four/Eight-Channel, 153.6 ksps, Low-Noise, 16-Bit Delta-Sigma ADCs with Internal Voltage Reference
PDF  118 Pages
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制造商  MICROCHIP [Microchip Technology]
网页  http://www.microchip.com
标志 MICROCHIP - Microchip Technology

MCP3461RT-E/ST 数据表(HTML) 30 Page - Microchip Technology

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MCP3461/2/4R
DS20006404C-page 30
 2020-2021 Microchip Technology Inc.
3.1
Differential Reference Voltage
Inputs: REFIN+/OUT, REFIN-
The REFIN+/OUT pin is the noninverting differential
reference input (VREF+) when VREF_SEL = 0. When
VREF_SEL = 1, it is the internal voltage reference out-
put voltage as well as the ADC voltage noninverting
reference pin.
The REFIN- pin is the inverting differential reference
input (VREF-).
For single-ended reference applications, the REFIN-
pin should be directly connected to AGND.
The differential reference voltage pins must respect
this condition at all times: 0.6V ≤ VREF ≤ AVDD. The
differential reference voltage input is given by the
following equation:
EQUATION 3-1:
For optimal ADC accuracy, appropriate bypass
capacitors should be placed between REFIN+/OUT
and AGND at all times. Using a 0.1 µF and a 10 µF
ceramic capacitor can help to decouple the reference
voltage around the sampling frequency (which would
lead to aliasing noise in the baseband). These bypass
capacitors are not mandatory for correct ADC opera-
tion, but removing these capacitors may degrade the
accuracy of the ADC.
3.2
Analog Inputs (CHn): Differential
or Single-Ended
The CHn pins are the analog input signal pins for the
ADC. Two analog multiplexers are used to connect the
CHn pins to the VIN+/VIN- analog inputs of the ADC.
Each multiplexer independently selects one input to be
connected to an ADC input (VIN+ or VIN-). Each CHn
pin can either be connected to the VIN+ or VIN- inputs
of the ADC. This multiplexer selection is controlled by
either the MUX register in MUX mode or the SCAN
register in Scan mode. See Figure 5-1 for more details
on the multiplexer structure.
When the input is selected by the multiplexer, the
differential (VIN) and Common-Mode Voltage (VINCOM)
at the ADC inputs are defined by:
EQUATION 3-2:
The input signal level is multiplied by the internal
programmable analog gain at the front end of the
Delta-Sigma
modulator.
For
single-ended
input
measurements, the user can select VIN- to be internally
connected to AGND.
The differential input voltage should not exceed an
absolute of ±VREF/Gain for accurate measurement. If
the input is out of range, the converter output code will
be saturated or overloaded depending on how the out-
put data format (DATA_FORMAT[1:0]) is selected. See
Section 5.6 “ADC Output Data Format” for further
information on the ADC output coding.
The absolute voltage on each of the analog signal
input pins can range from AGND – 0.1V to VDD + 0.1V.
Any voltage above or below this range will cause leak-
age currents through the Electrostatic Discharge
(ESD) diodes at the input pins. This ESD current can
cause unexpected performance of the device. The
Common-mode of the analog inputs should be chosen
such that both the differential analog input range and
the absolute voltage range on each pin are within the
specified operating range defined in the Electrical
Characteristics table.
3.3
SPI Serial Interface
Communication Pins
The SPI interface is compatible with both SPI Mode 0,0
and 1,1.
3.3.1
CHIP SELECT (CS)
This is the SPI Chip Select pin that enables/disables
the SPI serial communication. The CS falling edge
initiates the serial communication and the rising edge
terminates the communication. No communication can
take place when this pin is in a Logic High state. This
input is Schmitt Triggered.
3.3.2
SERIAL DATA CLOCK (SCK)
This is the serial clock input pin for SPI communication.
This input has a Schmitt Trigger structure. The maxi-
mum SPI clock speed is 20 MHz. Data are clocked into
the device on the rising edge of SCK. Data are clocked
out of the device on the falling edge of SCK. The device
interface is compatible with both SPI Mode 0,0 and 1,1.
SPI modes can be changed when CS is in Logic High
status.
SCK and MCLK are two different and asynchronous
clocks. SCK is only required during a communication,
while MCLK is continuously required when the part
converts analog inputs.
VREF
VREF+ VREF-
=
VIN
VIN+ VIN-
=
VINCOM
VIN+ VIN-
+
2
----------------------------------
=



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