MCP3461RT-ESLASHST datasheet(42/118 Pages) MICROCHIP

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MCP3461/2/4R

DS20006404C-page 42

 2020-2021 Microchip Technology Inc.

5.3.1

ANALOG GAIN

The gain settings, from 0.33x to 16x, are done in the

analog domain. This analog gain is placed on each ADC

differential input. Each doubling of the gain improves the

thermal noise due to sampling by approximately 3 dB,

which means the lowest noise configuration is obtained

when using the highest analog gain. The SNR, however,

is degraded, since doubling the gain factor reduces

the maximum allowable input signal amplitude by

approximately 6 dB.

If the gain is set to 0.33x, the differential input range

theoretically becomes ±3 * VREF. However, the device

does not support input voltages outside of the power

supply voltage range. If large reference voltages are

used with this gain, the input voltage range will be

clipped between AGND and AVDD, and therefore, the

output code span will be limited. This gain is useful

when the reference voltage is small and when the

input signal voltage is large.

The analog gain stage can be used to amplify very low

signals, but the differential input range of the

Delta-Sigma modulator must not be exceeded.

5.3.2

DIGITAL GAIN

When the gain setting is chosen from 16x to 64x, the

analog gain stays constant at 16x, and the additional

gain is done in the digital domain by a simple shift and

round of the output code. The digital gain range is

between 1x and 4x.

The output noise is approximately unchanged (except

for the quantization noise, which is slightly decreased).

The SNR is thus degraded by 6 dB per octave from 16x

to 64x settings.

This digital gain is useful for scaling up the signals with-

out using the host device (MCU) operations, but they

degrade the SNR and resolution (one bit per octave),

and do not significantly improve the noise performance,

except for very large OSR settings.

5.4

Delta-Sigma Modulator

5.4.1

ARCHITECTURE

The Delta-Sigma

 ADC includes a second-order

modulator with a multibit DAC architecture. Its 5-level

quantizer is a Flash ADC composed of four comparators

with equally spaced thresholds and a thermometer out-

put coding. The proprietary 5-level architecture ensures

minimum quantization noise at the outputs of the

modulators without disturbing the linearity or inducing

additional distortion.

Unlike most multibit DAC architectures, the 5-level

DAC used in this architecture is inherently linear, and

therefore, does not degrade the ADC linearity and THD

performance.

The sampling frequency is DMCLK; therefore, the

modulator outputs are refreshed at a DMCLK rate.

Figure 5-2 represents a simplified block diagram of the

Delta-Sigma modulator.

FIGURE 5-2:

Simplified Delta-Sigma ADC

Block Diagram.

5.4.2

MODULATOR OUTPUT BLOCK

The modulator output option enables users to apply

their own digital filtering on the output bit stream. By

setting IRQ_MODE[1] = 1 in the IRQ register, the mod-

ulator output is available at the IRQ/MDAT pin, at

AMCLK rate and also through the ADCDATA register

(0x0) with DMCLK rate. With this configuration, the

digital decimation filter is disabled in order to reduce

the current consumption and no data ready interrupt is

generated on any of the IRQ mechanisms. The

IRQ/MDAT pin is never placed in high-impedance

during the Modulator Output mode.

Since the Delta-Sigma modulator has a 5-level output

given by the state of four comparators with thermo-

meter coding, the output is represented using four bits,

each bit representing the state of the corresponding

comparator (see Table 5-4).

The comparator output bits are arranged serially at the

AMCLK rate on the IRQ/MDAT output pin (see

Figure 5-3).

This 1-bit serial bit stream is considered to be the same

one as is produced by a 1-bit DAC modulator with a

sampling frequency of AMCLK. The modulator can

either be considered as a 5-level output at DMCLK rate

or as 1-bit output at AMCLK rate. These two represen-

tations are interchangeable. The MDAT outputs can,

therefore, be used in any application that requires 1-bit

modulator outputs. This application can be integrated

with an external sinc filter or more advanced decima-

tion filters that are computed in the MCU or DSP

device.

When CLK_SEL[1:0] = 11 (internal oscillator with

external clock output), the AMCLK clock is present on

the MCLK pin. This configuration allows a correct

synchronization of the bit stream when the internal

oscillator is used as the master clock source.

When CLK_SEL[1:0] = 00, the modulator outputs are

also synchronized with the MCLK input, but the ratio

between MCLK and AMCLK must to be taken into

account in the user applications to correctly retrieve the

desired bit stream.

Differential Input

Voltage

(from Analog Mux)

Analog

nd Order

Loop

Filter

Output

Bitstream

Thermometer Coding

(to Digital Filter)

Delta-Sigma 2

nd Order 5-Level Modulator

Analog

Digital

5-Level DAC

Quantizer

5-Level Flash

ADC

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