MCP661 datasheet(21/68 Pages) MICROCHIP

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DS20002194E-page 21

MCP660/1/2/3/4/5/9

4.0

APPLICATIONS

The MCP660/1/2/3/4/5/9 family is manufactured using

the Microchip state-of-the-art CMOS process. It is

designed for low-cost, low-power and high-speed

applications. Its low supply voltage, low quiescent

current

and

wide

bandwidth

make

the

MCP660/1/2/3/4/5/9

ideal

for

battery-powered

applications.

4.1

Input

4.1.1

PHASE REVERSAL

The input devices are designed to not exhibit phase

inversion when the input pins exceed the supply

voltages.

Figure 2-39 shows

input voltage

exceeding both supplies with no phase inversion.

4.1.2

INPUT VOLTAGE AND CURRENT

LIMITS

The electrostatic discharge (ESD) protection on the

inputs can be depicted as shown in Figure 4-1. This

structure was chosen to protect the input transistors

and to minimize input bias current (IB). The input ESD

diodes clamp the inputs when they try to go more than

one diode drop below VSS. They also clamp any

voltages that go too far above VDD; their breakdown

voltage is high enough to allow normal operation and

low enough to bypass quick ESD events within the

specified limits.

FIGURE 4-1:

Simplified Analog Input ESD

Structures.

In order to prevent damage and/or improper operation

of these amplifiers, the circuit must limit the currents

(and voltages) at the input pins (see Section 1.1

“Absolute Maximum Ratings †”). Figure 4-2 shows

the recommended approach to protecting these inputs.

The internal ESD diodes prevent the input pins (VIN+

and VIN-) from going too far below ground, while the

resistors R1 and R2 limit the possible current drawn out

of the input pins. Diodes D1 and D2 prevent the input

pins (VIN+ and VIN-) from going too far above VDD and

dump any currents onto VDD.

When implemented as shown, resistors R1 and R2 also

limit the current through D1 and D2.

FIGURE 4-2:

Protecting the Analog

Inputs.

It is also possible to connect the diodes to the left of the

resistors R1 and R2. If so, the currents through the

diodes D1 and D2 need to be limited by some other

mechanism. The resistors then serve as in-rush current

limiters; the DC current into the input pins (VIN+ and

VIN-) should be very small.

A significant amount of current can flow out of the

inputs

(through

the

ESD

diodes)

when

the

common-mode voltage (VCM) is below ground (VSS);

see Figure 2-13. Applications that are high-impedance

may need to limit the usable voltage range.

4.1.3

NORMAL OPERATION

The input stage of the MCP660/1/2/3/4/5/9 op amps

uses a differential PMOS input stage. It operates at low

common-mode input voltages (VCM), with VCM

between VSS – 0.3V and VDD – 1.3V. To ensure proper

operation, the input offset voltage (VOS) is measured at

both VCM =VSS – 0.3V and VCM =VDD –1.3V. See

Figures 2-5 and 2-6 for temperature effects.

When operating at very low non-inverting gains, the

output voltage is limited at the top by the VCM range

(< VDD – 1.3V); see Figure 4-3.

FIGURE 4-3:

Unity-Gain Voltage

Limitations for Linear Operation.

Bond

Pad

Bond

Pad

Bond

Pad

VDD

VIN+

VSS

Input

Stage

Bond

Pad

VIN-

VDD

VOUT

MCP66X

minimum expected V



–

2mA

------------------------------------------------------------------------



minimum expected V



–

2mA

------------------------------------------------------------------------



VIN

VDD

VOUT

MCP66X



OUT

1.3V

–



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