Data Sheet

HMC8108

Rev. 0 | Page 5 of 18

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

17

1

3

4

2

NIC

NIC

LNA_VG1

NIC

5

6

RFIN

NIC

7

VCTRL

8

NIC

NIC

HMC8108

TOP VIEW

(Not to Scale)

EPAD

NOTES

1. NIC = NOT INTERNALLY CONNECTED.

2. EXPOSED PAD. EXPOSED PAD MUST

BE CONNECTED TO RF/DC GROUND.

Figure 2. Pin Configuration

Table 4. Pin Function Descriptions

Pin No.

Mnemonic

Description

1, 2, 4, 6, 8, 9, 11, 12,

14, 17 to 19, 21, 22,

24, 25, 27, 29, 31

NIC

No Internal Connection. These pins are not connected internally.

3

LNA_VG1

Gate Bias Voltage for the First Low Noise Amplifier. See Figure 3 for the interface schematic.

5

RFIN

Radio Frequency Input. This pin is dc-coupled and matched to 50 Ω. See Figure 4 for the interface

schematic.

7

VCTRL

Voltage Control. Gate bias attenuation control for the low noise amplifier. See Figure 5 for the interface

schematic.

10

LNA_VG2

Gate Bias Voltage for the Second Low Noise Amplifier. See Figure 6 for the interface schematic.

13, 28

IF_I, IF_Q

In-Phase and Quadrature Intermediate Frequency Output Pins. See Figure 7 for the interface schematic.

15

MIX_VG

Gate Bias Voltage for FET Mixer. See Figure 8 for the interface schematic.

16

BUFF_VG

Gate Bias Voltage for the Local Oscillator Buffer. See Figure 9 for the interface schematic.

20

LOIN

Local Oscillator Input. This pin is ac-coupled and matched to 50 Ω. See Figure 10 for the interface schematic.

23

BUFF_VD

Drain Bias Voltage for the Local Oscillator Buffer. See Figure 11 for the interface schematic.

26

GND

Ground Connect. This pin must be connected to RF/dc ground. See Figure 12 for the interface schematic.

30

LNA_VD2

Drain Bias Voltage for the Second Low Noise Amplifier. See Figure 13 for the interface schematic.

32

LNA_VD1

Drain Bias Voltage for the First Low Noise Amplifier. See Figure 14 for the interface schematic.

EPAD

Exposed Pad. Connect the exposed pad to RF/dc ground. See Figure 12 for the interface schematic.