Data Sheet

HMC8108

Rev. 0 | Page 17 of 18

EVALUATION BOARD INFORMATION

RF circuit design techniques were implemented for the evaluation

board PCB shown in Figure 58. Signal lines have 50 Ω impedance,

and the package ground leads and exposed pad are connected

directly to the ground plane. A sufficient number of via holes

connect the top and bottom ground planes. The full evaluation

circuit board shown in Figure 58 is available from Analog Devices,

Inc., upon request.

Figure 58. EV1HMC8108LC5 Evaluation PCB Top Layer

Table 5. Bill of Material for the EV1HMC8108LC5 Evaluation PCB

Reference Designator

Quantity

Description

600-01494-00-1

1

Evaluation board PCB; circuit board material: Rogers 4350 or Arlon 25FR

J1, J2

2

SMA connectors, SRI

J3, J7

2

SMA connectors, Johnson

J4

1

Connector header, 2 mm ,12-position vertical, SMT

J5, J6

2

Terminal strips, single row, 3-pin, SMT

C1

1

Ceramic capacitor, 0.5 pF, 50 V, C0G, 0402

C2 to C12

11

Ceramic capacitors, 0.6 pF, ±0.1 pF, 50 V, C0G, 0402

C13 to C16, C18 to C21

8

Ceramic capacitors, 1 nF, 50 V, X7R, 0402

C22 to C29

8

Ceramic capacitors, 10 nF, 50 V, 10%, X7R, 0402

C30 to C32

3

Ceramic capacitors, 100 nF, 16 V, 10%, X7R, 0402

L1 to L3

3

Inductors, 5.6 nH, 0402, ±5%, 760 mA

TP1 to TP3

3

Test points, PC compact, SMT

U1

1

Device under test (DUT), HMC8108LC5