MIC2104 datasheet(33/42 Pages) MICROCHIP

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DS20005899A-page 33

MIC2103/4

6.0

PCB LAYOUT GUIDELINES

PCB Layout is critical to achieve reliable, stable and

efficient performance. A ground plane is required to

control EMI and minimize the inductance in power and

signal return paths.

The following guidelines should be followed to insure

proper operation of the MIC2103/4 buck controllers.

6.1

• The 1 µF ceramic capacitors, which are

connected to the VDD and PVDD pins, must be

located right at the IC. The VDD pin is very noise

sensitive and placement of the capacitor is very

critical. Use wide traces to connect to the VDD,

PVDD, AGND, and PGND pins.

• The signal ground pin (AGND) must be connected

directly to the ground planes. Do not route the

AGND pin to the PGND pin on the top layer.

• Place the IC close to the point of load (POL).

• Use fat traces to route the input and output power

lines.

• Signal and power grounds should be kept

separate and connected at only one location.

6.2

Input Capacitor

• Place the input capacitors on the same side of the

board and as close to the MOSFETs as possible.

• Place several vias to the ground plane close to

the input capacitor ground terminal.

• Use either X7R or X5R dielectric ceramic input

capacitors. Do not use Y5V or Z5U type

capacitors.

• Do not replace the ceramic input capacitor with

any other type of capacitor. Any type of capacitor

can be placed in parallel with the input capacitor.

• If a Tantalum input capacitor is placed in parallel

with the input capacitor, it must be recommended

for switching regulator applications and the

operating voltage must be derated by 50%.

• In “Hot-Plug” applications, a Tantalum or

Electrolytic bypass capacitor must be used to limit

the over-voltage spike seen on the input supply

with power is suddenly applied.

6.3

RC Snubber

• Place the RC snubber on the same side of the

board and as close to the SW pin as possible.

6.4

Inductor

• Keep the inductor connection to the switch node

(SW) short.

• Do not route any digital lines underneath or close

to the inductor.

• Keep the switch node (SW) away from the

feedback (FB) pin.

• The SW pin should be connected directly to the

drain of the low-side MOSFET to accurately

sense the voltage across the low-side MOSFET.

• To minimize noise, place a ground plane

underneath the inductor.

6.5

Output Capacitor

• Use a wide trace to connect the output capacitor

ground terminal to the input capacitor ground

terminal.

• Phase margin will change as the output capacitor

value and ESR changes. Contact the factory if the

output capacitor is different from what is shown in

the BOM.

• The feedback trace should be separate from the

power trace and connected as close as possible

to the output capacitor. Sensing a long

high-current load trace can degrade the DC load

regulation.

6.6

MOSFETs

• Low-side MOSFET gate drive trace (DL pin to

MOSFET gate pin) must be short and routed over

a ground plane. The ground plane should be the

connection between the MOSFET source and

PGND.

• Choose a low-side MOSFET with a high CGS/CGD

ratio and a low internal gate resistance to

minimize the effect of dv/dt inducted turn-on.

• Do not put a resistor between the low-side

MOSFET gate drive output and the gate.

• Use a 4.5V VGS rated MOSFET. Its higher gate

threshold voltage is more immune to glitches than

a 2.5V or 3.3V rated MOSFET. MOSFETs that are

rated for operation at less than 4.5V VGS should

not be used.

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