Data Sheet

HMC6505A

Rev. 0 | Page 5 of 30

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

HMC6505A

TOP VIEW

(Not to Scale)

1

3

4

2

NIC

NIC

NIC

NIC

5

6

VDD1

NIC

7

LOIN

8

GND

17 NIC

18 VDD3

19 NIC

20 NIC

21 NIC

22 NIC

23 VDD2

24 NIC

NOTES

1. NOT INTERNALLY CONNECTED. THESE PINS

ARE NOT CONNECTED INTERNALLY. HOWEVER,

PINS MAY BE CONNECTED TO RF/DC GROUND

WITHOUT AFFECTING PERFORMANCE.

2. EXPOSED PAD. CONNECT TO A LOW IMPEDANCE

THERMAL AND ELECTRICAL GROUND PLANE.

Figure 2. Pin Configuration

Table 4. Pin Function Descriptions

Pin No.

Mnemonic

Description

1 to 4, 6, 9 to 11, 16,

17, 19 to 22, 24,

25, 32

NIC

Not Internally Connected. These pins are not connected internally. However, pins may be connected

to RF/dc ground without affecting performance.

5

VDD1

Power Supply Voltage for LO Amplifier. See Figure 3 for the interface schematic. Refer to the typical

application circuit (see Figure 103) for the required external components.

7

LOIN

Local Oscillator Input. See Figure 4 for the interface schematic. This pin is ac-coupled and matched

to 50 Ω.

8, 13, 15, 27, 29, 31

GND

Ground Connect. See Figure 5 for the interface schematic. These pins and package bottom must be

connected to RF/dc ground.

12

VGG

Gate Voltage for the Variable Gain Amplifier. See Figure 6 for the interface schematic. Refer to the

typical application circuit (see Figure 103) for the required external components.

14

RFOUT

Radio Frequency Output. See Figure 7 for the interface schematic. This pin is ac-coupled and

matched to 50 Ω.

18, 23

VDD3, VDD2

Power Supply Voltage for the Variable Gain Amplifier. See Figure 8 for the interface schematic. Refer

to the typical application circuit (see Figure 103) for the required external components.

26

VCTRL

Gain Control Voltage for the Variable Gain Amplifier. See Figure 9 for the interface schematic. Refer to

the typical application circuit (see Figure 103) for the required external components.

28, 30

IF1, IF2

Quadrature Intermediate Frequency Inputs. See Figure 10 for the interface schematic. For applications

not requiring operation to dc, use an off chip dc blocking capacitor. For operation to dc, these pins

must not source or sink more than ±3 mA of current or device malfunction and failure can result.

EPAD

Exposed Pad. Connect to a low impedance thermal and electrical ground plane.