Power Losses at 32 KHz

Switching Time Inductive Load at 32 KHz

(see figure 2)

In order to saturate the power switch and reduce

conduction losses, adequate direct base current

100

turn off the power transistor (retrace phase).

Most

of

the

dissipation,

in

the

deflection

application, occurs at switch-off. Therefore it is

minimizes

power

losses,

fall

time

and,

32 KHz and

64KHz scanning frequencies for choosing the

optimum negative drive. The test circuit is

illustrated in figure 1.

excess carrier in the collector when base current

is still present, this would avoid any tailing

phenomenon in the collector current.

The values of L and C are calculated from the

following equations:

1

2

L

1

2

C

ω= 2 πf =

1

√

flyback voltage, f= frequency of oscillation during

retrace.

BASE DRIVE INFORMATION

Reverse Biased SOA

BUH313

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