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PIMXRT516SCVP2A 数据表(PDF) 86 Page - NXP Semiconductors

部件名 PIMXRT516SCVP2A
功能描述  i.MX RT1170 Crossover Processors Data Sheet for Consumer Products
PDF  128 Pages
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制造商  NXP [NXP Semiconductors]
网页  http://www.nxp.com
标志 NXP - NXP Semiconductors

PIMXRT516SCVP2A 数据表(HTML) 86 Page - NXP Semiconductors

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i.MX RT1170 Crossover Processors Data Sheet for Consumer Products, Rev. 1, 05/2021
86
NXP Semiconductors
Electrical characteristics
4.9.1
LPSPI timing parameters
The Low Power Serial Peripheral Interface (LPSPI) provides a synchronous serial bus with master and
slave operations. Many of the transfer attributes are programmable. The following tables provide timing
characteristics for classic LPSPI timing modes.
All timing is shown with respect to 20% VDD and 80% VDD thresholds, unless noted, as well as input
signal transitions of 3 ns and a 30 pF maximum load on all LPSPI pins.
Figure 35. LPSPI Master mode timing (CPHA = 0)
Table 82. LPSPI Master mode timing
Number
Symbol
Description
Min.
Max.
Units
Note
1fSCK
Frequency of operation
—
fperiph / 2
MHz
1
1 Absolute maximum frequency of operation (fop) is 30 MHz. The clock driver in the LPSPI module for fperiph must guaranteed
this limit is not exceeded.
2tSCK
SCK period
2 x tperiph
—ns
2
2 tperiph = 1000 / fperiph
3tLead
Enable lead time
1
—
tperiph
—
4tLag
Enable lag time
1
—
tperiph
—
5tWSCK
Clock (SCK) high or low time
tSCK / 2 - 3
—
ns
—
6tSU
Data setup time (inputs)
10
—
ns
—
7tHI
Data hold time (inputs)
2
—
ns
—
8tV
Data valid (after SCK edge)
—
8
ns
—
9tHO
Data hold time (outputs)
0
—
ns
—
(OUTPUT)
2
8
6
7
MSB IN
2
LSB IN
MSB OUT
2
LSB OUT
9
5
5
3
(CPOL=0)
4
SCK
SCK
(CPOL=1)
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
1. If configured as an output.
PCS
1
(OUTPUT)
(OUTPUT)
SOUT
(OUTPUT)
SIN
(INPUT)
BIT 6 . . . 1
BIT 6 . . . 1



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