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SC3200 数据表(PDF) 51 Page - Advanced Micro Devices |
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SC3200 数据表(HTML) 51 Page - Advanced Micro Devices |
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51 / 447 page ![]() AMD Geode™ SC3200 Processor Data Book 51 Signal Definitions Revision 5.1 AF2 IDE_CS0# O O1/4 VIO PMR[24] = 0 TFTD5 O O1/4 PMR[24] = 1 AF3 SOUT1 O O8/8 VIO --- CLKSEL1 I (PD100) INSTRP Strap (See Table 3- 6 on page 58.) AF4 OVER_CUR# I INTS VIO --- AF285 MD50 I/O INT, TS2/5 VIO --- AF295 MD49 I/O INT, TS2/5 VIO --- AF305 MD54 I/O INT, TS2/5 VIO --- AF315 MD53 I/O INT, TS2/5 VIO --- AG1 GPIO18 I/O (PU22.5) INTS, O8/8 VIO PMR[16] = 0 DTR1#/BOUT1 O (PU22.5) O8/8 PMR[16] =1 AG2 SIN1 I INTS VIO --- AG3 X27I I WIRE VIO --- AG4 TEST1 O O2/5 VIO PMR[29] = 1 PLL6B I/O INTS, TS2/5 PMR[29] = 0 AG285 MD21 I/O INT, TS2/5 VIO --- AG29 DQM6 O O2/5 VIO --- AG30 DQM2 O O2/5 VIO --- AG315 MD55 I/O INT, TS2/5 VIO --- AH1 POWER_EN O O1/4 VIO --- AH2 X27O O WIRE VIO --- AH3 TEST0 O O2/5 VIO PMR[29] = 1 PLL2B I/O INT, TS2/5 PMR[29] = 0 AH4 VIO PWR --- --- --- AH5 PWRBTN# I (PU100) INBTN VSB --- AH6 GPWIO0 I/O (PU100) INTS, TS2/14 VSB --- AH7 VSS GND --- --- --- AH8 CLK32 O O2/5 VSB --- AH9 POR# I INTS VIO --- AH105 MD3 I/O INT, TS2/5 VIO --- AH115 MD5 I/O INT, TS2/5 VIO --- AH12 WEA# O O2/5 VIO --- AH13 VSS GND --- --- --- AH14 VIO PWR --- --- --- Ball No. Signal Name I/O (PU/PD) Buffer1 Type Power Rail Configuration AH15 MA1 O O2/5 VIO --- AH165 MD34 I/O INT, TS2/5 VIO --- AH175 MD37 I/O INT, TS2/5 VIO --- AH18 VIO PWR --- --- --- AH19 VSS GND --- --- --- AH205 MD41 I/O INT, TS2/5 VIO --- AH21 MA9 O O2/5 VIO --- AH22 MA8 O O2/5 VIO --- AH23 DQM1 O O2/5 VIO --- AH245 MD13 I/O INT, TS2/5 VIO --- AH25 VSS GND --- --- --- AH26 MA11 O O2/5 VIO --- AH27 CS1# O O2/5 VIO --- AH285 MD18 I/O INT, TS2/5 VIO --- AH295 MD48 I/O INT, TS2/5 VIO --- AH305 MD20 I/O INT, TS2/5 VIO --- AH315 MD51 I/O INT, TS2/5 VIO --- AJ1 TEST2 O O2/5 VIO PMR[29] = 1 PLL5B I/O INT, TS2/5 PMR[29] = 0 AJ2 X32I I WIRE VBAT --- AJ3 X32O O WIRE VBAT --- AJ4 VPLL3 PWR --- --- --- AJ55, 2 ONCTL# O OD14 VSB --- AJ6 GPWIO2 I/O (PU100) INTS, TS2/14 VSB --- AJ7 VIO PWR --- --- --- AJ8 GPIO11 I/O (PU22.5) INTS, O8/8 VIO PMR[18] = 0 and PMR[8] = 0 RI2# I (PU22.5) INTS PMR[18] = 1 and PMR[8] = 0 IRQ15 I (PU22.5) INTS1 PMR[18] = 0 and PMR[8] = 1 AJ95 MD0 I/O INT, TS2/5 VIO --- AJ10 VIO PWR --- --- --- AJ115 MD6 I/O INT, TS2/5 VIO --- AJ12 CASA# O O2/5 VIO --- AJ13 BA0 O O2/5 VIO --- AJ14 MA10 O O2/5 VIO --- Ball No. Signal Name I/O (PU/PD) Buffer1 Type Power Rail Configuration Table 3-4. 481-TEPBGA Ball Assignment - Sorted by Ball Number (Continued) |
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