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PIMXRT516SCVM5A 数据表(PDF) 55 Page - NXP Semiconductors |
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PIMXRT516SCVM5A 数据表(HTML) 55 Page - NXP Semiconductors |
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55 / 128 page  Electrical characteristics i.MX RT1170 Crossover Processors Data Sheet for Consumer Products, Rev. 1, 05/2021 NXP Semiconductors 55 4.4.2 WDOG reset timing parameters Figure 10 shows the WDOG reset timing and Table 42 lists the timing parameters. Figure 10. WDOGn_B timing diagram NOTE RTC_XTALI is approximately 32 kHz. RTC_XTALI cycle is one period or approximately 30 s. NOTE WDOGn_B output signals (for each one of the Watchdog modules) do not have dedicated pins, but are muxed out through the IOMUX. See the IOMUX manual for detailed information. Table 41. POR reset timing parameters ID Parameter Min Max Unit CC1 Duration of POR_B to be qualified as valid. 1 — RTC_XTALI cycle Table 42. WDOGn_B timing parameters ID Parameter Min Max Unit CC3 Duration of WDOGn_B Assertion 1 — RTC_XTALI cycle WDOGn_B CC3 (Output) |
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