LTC1983-3/LTC1983-5

8

sn1983 1983fs

Inrush Currents

sients in the several hundred milliamp range whenever the

charge pump is enabled. During start-up, these inrush

currents may approach 1 to 2 amps. For this reason, it is

important to minimize the source resistance between the

may result in regulation problems or even prevent start-

up. One way that this can be avoided (especially when the

source impedance can’t be lowered due to system con-

need to add 1

µF to 10µF tantalum capacitor in parallel to

limit input voltage transients. Input voltage transients will

of this situation is in USB applications.

Ultralow Quiescent Current Regulated Supply

The LTC1983 contains an internal resistor divider (refer to

the Block Diagram) that draws only 1

µA (typ for the 3V

down, the resistor divider is disconnected from the output

and the part draws only leakage current from the output.

During no-load conditions, applying a 1Hz to 100Hz, 2%

to 5% duty cycle signal to the SHDN pin ensures that the

circuit of Figure 2 comes out of shutdown frequently

enough to maintain regulation even under low-load condi-

tions. Since the part spends nearly all of its time in

shutdown, the no-load quiescent current is essentially

zero. However, the part will still be in operation during the

time the SHDN pin is high, so the current will not be zero

and can be calculated using the following equations to

[(Time out of shutdown) • (Burst Mode operation quies-

being charged before the LTC1983 enters Burst Mode

operation)]/(Period of SHDN signal). This number will be

highly dependent on the amount of board leakage current

draw some leakage current) and must be calculated and

verified for each different board design.

The LTC1983 must be out of shutdown for a minimum

duration of 200

µstoallowenoughtimetosensetheoutput

and keep it in regulation. A 1Hz, 2% duty cycle signal will

though the term no-load is used, there will always be board

leakage current and leakage current drawn by anything

part up every once in a while to verify regulation. As the

part is taken out of shutdown must also be increased to

version) during the OFF phase (see Figure 3). A 100Hz, 2%

duty cycle signal on the SHDN pin ensures proper regula-

tion with load currents as high as 100

µA. When load

current greater than 100

µA is needed, the SHDN pin must

be forced high as in normal operation.

Each time the LTC1983 comes out of shutdown, the part

delivers a minimum of one clock cycle worth of charge to

conditions, this behavior may cause a net excess of charge

to be delivered to the output capacitor if a high frequency

signal is used on the SHDN pin (e.g., 50Hz to 100Hz).

may even go out of regulation. To avoid this potential

Figure 2. Ultralow Quiescent Current Regulated Supply

GND

SHDN

LTC1983-3

1

µF

CERAMIC

FROM MPU

SHDN

10

µF

TANTALUM

10

µF

CERAMIC

SHDN PIN WAVEFORMS:

(1Hz TO 100Hz, 2% TO 5% DUTY CYCLE)

–3V

± 4%

1983 F02

3.3V TO 5.5V

OPERATIO

(Refer to Block Diagram)