3.

Pins

The PD69210 and PD69220 controller each has 32 pins, which are described in this section.

3.1

Pin Diagrams

The following figures represent the top view of PD69210 and PD69220 devices.

Figure 3-1. PD69210 and PD69220 Pin Diagram

Note: For definitions about markings in the pinout diagram, see Ordering Information.

3.2

Pin Descriptions

The following table describes the functional pin descriptions of the PD69210 and PD69220 devices.

Table 3-1. Pin Descriptions

PD69210

Pin

PD69220

Pin

Designation

Type

Description

1

1

Reserved

OUT

Reserved UART. Leave open.

2

2

Reserved

IN

Reserved UART. Pull up to 3.3 V via 10 kΩ.

3

32

xSys_OK/LED System OK

OUT

System validity indication. The behavior of this

output is controlled by individual software

mask. (Active Low)

4

31

xDISABLE_PORTS

IN

Disable all PoE ports. When this input is

asserted low, the controller shuts down all PoE

ports in the system.

See AN3361 for pin connection requirements.

(Active Low)

5

6

ESPI_MISO

IN

ESPI bus to PoE manager. SPI master in, slave

out. SPI packets are received on this line.

PD69210/PD69220

Pins

Datasheet

DS00003424A-page 8