4.4

Recommended PCB Layout

The following figures show the recommended PCB layout pattern for the 32-pin QFN 5 mm × 5 mm PD69210 and for

the 32-pin LGA 5 mm × 5 mm PD69220. Units are in mm.

Figure 4-3. PD69210 and PD69220 Top-Layer Copper PCB Layout

The recommended solder paste stencil for the PD69220 is different than the recommended stencil for PD69200.

Figure 4-4. PD69210 Top-Layer Solder Paste and Vias PCB Layout for Thermal Pad Array

Note: The contract manufacturer has latitude to modify the solder paste stencil for manufacturability reasons. The

solder paste stencil covers 65% to 80% of the thermal pad and must not allow solder to be applied to the thermal vias

under the QFN package using any method they deem appropriate. Any design should be subject to system validation

and qualification prior to commitment to mass production of field deployment. Use a 5 mil stencil.

PD69210/PD69220

Package Information

Datasheet

DS00003424A-page 14