®

AS7C33256PFS16A

AS7C33256PFS18A

3/14/01; V.1.0

Alliance Semiconductor

P. 3 of 11

Signal descriptions

Absolute maximum ratings

Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional

operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to

absolute maximum rating conditions may affect reliability.

Signal

I/O

Properties

Description

CLK

I

CLOCK

Clock. All inputs except OE, FT, ZZ, LBO are synchronous to this clock.

A0–A17

I

SYNC

Address. Sampled when all chip enables are active and ADSC or ADSP are asserted.

DQ[a,b]

I/O

SYNC

Data. Driven as output when the chip is enabled and OE is active.

CE0

ISYNC

Master chip enable. Sampled on clock edges when ADSP or ADSC is active. When

CE0 is inactive, ADSP is blocked. Refer to the Synchronous Truth Table for more

information.

CE1, CE2

ISYNC

Synchronous chip enables. Active HIGH and active LOW, respectively. Sampled on

clock edges when ADSC is active or when CE0 and ADSP are active.

ADSP

ISYNC

Address strobe (processor). Asserted LOW to load a new address or to enter

standby mode.

ADSC

ISYNC

Address strobe (controller). Asserted LOW to load a new address or to enter

standby mode.

ADV

I

SYNC

Burst advance. Asserted LOW to continue burst read/write.

GWE

ISYNC

Global write enable. Asserted LOW to write all 16/18 bits. When HIGH, BWE and

BW[a,b] control write enable.

BWE

ISYNC

Byte write enable. Asserted LOW with GWE = HIGH to enable effect of BW[a,b]

inputs.

BW[a,b]

ISYNC

Write enables. Used to control write of individual bytes when GWE = HIGH and

BWE = LOW. If any of BW[a,b] is active with GWE = HIGH and BWE = LOW the

cycle is a write cycle. If all BW[a,b] are inactive, the cycle is a read cycle.

OE

IASYNC

Asynchronous output enable. I/O pins are driven when OE is active and the chip is

in read mode.

LBO

I

STATIC default =

HIGH

Count mode. When driven HIGH, count sequence follows Intel XOR convention.

When driven LOW, count sequence follows linear convention. This signal is

internally pulled HIGH.

FT

ISTATIC

Flow-through mode.When LOW, enables single register flow-through mode.

ZZ

I

ASYNC

Sleep. Places device in low power mode; data is retained. Connect to GND if

unused.

Parameter

Symbol

Min

Max

Unit

Power supply voltage relative to GND

–0.5

+4.6

V

Input voltage relative to GND (input pins)

–0.5

V

Input voltage relative to GND (I/O pins)

–0.5

V

Power dissipation

–1.8

W

DC output current

–50

mA

Storage temperature (plastic)

–65

+150

°C

Temperature under bias

–65

+135

°C