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AS7C33256PFS18A 数据表(PDF) 4 Page - Alliance Semiconductor Corporation

部件名 AS7C33256PFS18A
功能描述  3.3V 256K 횞 16/18 pipeline burst synchronous SRAM
PDF  11 Pages
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制造商  ALSC [Alliance Semiconductor Corporation]
网页  https://www.alliancememory.com
标志 ALSC - Alliance Semiconductor Corporation

AS7C33256PFS18A 数据表(HTML) 4 Page - Alliance Semiconductor Corporation

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AS7C33256PFS16A
AS7C33256PFS18A
®
3/14/01; V.1.0
Alliance Semiconductor
P. 4 of 11
Synchronous truth table
Key: X = Don’t Care, L = Low, H = High.
1See “Write enable truth table” on page 2 for more information.
2
Q in flow through mode
3
For write operation following a READ,
OE must be HIGH before the input data set up time and held HIGH throughout the input hold
time.
Recommended operating conditions
CE0
CE1
CE2
ADSP
ADSC
ADV
WEn1
OE
Address accessed
CLK
Operation
DQ
H
X
X
X
L
X
X
X
NA
L to H
Deselect
Hi
−Z
L
L
X
L
X
X
X
X
NA
L to H
Deselect
Hi
−Z
L
L
X
H
L
X
X
X
NA
L to H
Deselect
Hi
−Z
L
X
H
L
X
X
X
X
NA
L to H
Deselect
Hi
−Z
L
X
H
H
L
X
X
X
NA
L to H
Deselect
Hi
−Z
L
H
L
L
X
X
X
L
External
L to H
Begin read
Hi
−Z2
L
H
L
L
X
X
X
H
External
L to H
Begin read
Hi
−Z
L
H
L
H
L
X
F
L
External
L to H
Begin read
Hi
−Z2
L
H
L
H
L
X
F
H
External
L to H
Begin read
Hi
−Z
X
X
X
H
H
L
F
L
Next
L to H
Cont. read
Q
X
X
X
H
H
L
F
H
Next
L to H
Cont. read
Hi
−Z
X
X
X
H
H
H
F
L
Current
L to H
Suspend read
Q
X
X
X
H
H
H
F
H
Current
L to H
Suspend read
Hi
−Z
H
X
X
X
H
L
F
L
Next
L to H
Cont. read
Q
H
X
X
X
H
L
F
H
Next
L to H
Cont. read
Hi
−Z
H
X
X
X
H
H
F
L
Current
L to H
Suspend read
Q
H
X
X
X
H
H
F
H
Current
L to H
Suspend read
Hi
−Z
L
H
L
H
L
X
T
X
External
L to H
Begin write
D3
X
X
X
H
H
L
T
X
Next
L to H
Cont. write
D
H
X
X
X
H
L
T
X
Next
L to H
Cont. write
D
X
X
X
H
H
H
T
X
Current
L to H
Suspend write
D
H
X
X
X
H
H
T
X
Current
L to H
Suspend write
D
Parameter
Symbol
Min
Nominal
Max
Unit
Supply voltage
VDD
3.135
3.3
3.6
V
VSS
0.0
0.0
0.0
3.3V I/O supply
voltage
VDDQ
3.135
3.3
3.6
V
VSSQ
0.0
0.0
0.0
2.5V I/O supply
voltage
VDDQ
2.35
2.5
2.9
V
VSSQ
0.0
0.0
0.0
Input voltages†
Address and
control pins
VIH
2.0
–
VDD + 0.3
V
VIL
–0.5*
* VIL min = –2.0V for pulse width less than 0.2 × tRC.
† Input voltage ranges apply to 3.3V I/O operation. For 2.5V I/O operation, contact factory for input specifications.
–0.8
I/O pins
VIH
2.0
–
VDDQ + 0.3
V
VIL
–0.5*
–0.8
Ambient operating temperature
TA
0–
70
°C



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