THS1007

SLAS286A – AUGUST 2000– REVISED DECEMBER 2002

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17

Sample N

Channel 1, 2

Sample N+1

Channel 1, 2

Sample N+2

Channel 1, 2

Sample N+3

Channel 1, 2

Data N–1

Channel 2

Data N

Channel 1

Data N

Channel 2

Data N+1

Channel 1

Data N–2

Channel 1

Data N–2

Channel 2

Data N–1

Channel 1

AIN

CONV_CLK

READ†

†READ is the logical combination from CS0, CS1 and RD

SYNC

td(A)

td(pipe)

tw(CONV_CLKH)

tw(CONV_CLKL)

tc

tsu(CONV_CLKL-READL)

tsu(READH-CONV_CLKL)

td(CONV_CLKL-SYNCL)

td(CONV_CLKL-SYNCH)

Figure 29. Conversion Timing in 2-Channel Operation

Figure 30 shows the conversion timing when three analog input channels are selected. The maximum

throughput rate per channel is 2 MSPS in this mode. The data flow in the bottom of the figure shows in which

order the converted data is available to the data bus. The SYNC signal is active low when the data of channel

one is available to the data bus. The data of channel one is followed by the data of channel two and channel

three before channel one is again available and the SYNC signal is active low.

Sample N

Channel 1, 2, 3

Sample N+1

Channel 1, 2, 3

Sample N+2

Channel 1, 2, 3

Data N–1

Channel 3

Data N

Channel 1

Data N

Channel 2

Data N

Channel 3

Data N–2

Channel 3

Data N–1

Channel 1

Data N–1

Channel 2

AIN

CONV_CLK

READ†

†READ is the logical combination from CS0, CS1 and RD

SYNC

td(A)

td(pipe)

tw(CONV_CLKH)

tw(CONV_CLKL)

tc

tsu(CONV_CLKL-READL)

tsu(READH-CONV_CLKL)

td(CONV_CLKL-SYNCL)

td(CONV_CLKL-SYNCH)

Figure 30. Conversion Timing in 3-Channel Operation