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THS1007IDA 数据表(PDF) 18 Page - Texas Instruments |
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THS1007IDA 数据表(HTML) 18 Page - Texas Instruments |
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18 / 36 page ![]() THS1007 SLAS286A – AUGUST 2000– REVISED DECEMBER 2002 www.ti.com 18 Figure 31 shows the conversion timing when four analog input channels are selected. The maximum throughput rate per channel is 1.5 MSPS in this mode. The data flow in the bottom of the figure shows in which order the converted data is available to the databus. The SYNC signal is active low when the data of channel one is available to the data bus. The data of channel one is followed by the data of channel two, the data of channel three and the data of channel four before channel one is again available to the databus and SYNC is active low. Sample N Channel 1, 2, 3, 4 Sample N+1 Channel 1, 2, 3, 4 Data N–1 Channel 4 Data N Channel 1 Data N Channel 2 Data N Channel 3 Data N–1 Channel 1 Data N–1 Channel 2 Data N–1 Channel 3 AIN CONV_CLK READ† †READ is the logical combination from CS0, CS1 and RD SYNC td(A) td(pipe) tw(CONV_CLKH) tw(CONV_CLKL) tc tsu(CONV_CLKL-READL) tsu(READH-CONV_CLKL) tsu(CONV_CLKL-SYNCH) tsu(CONV_CLKL-SYNCL) Figure 31. Timing of Continuous Conversion Mode (4-channel operation) |
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