PLL601-01

Low Phase Noise PLL Clock Multiplier

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/03/04 Page 2

PIN DESCRIPTIONS

MULTIPLIER SELECT TABLE

S3

S2

S1

S0

CLK

0

0

0

0

Test

0

0

0

1

Input x 11

0

0

1

0

Input x 1

0

0

1

1

Input x 3

0

1

0

0

Input x 4

0

1

0

1

Input x 5

0

1

1

0

Input x 6

0

1

1

1

Input x 8

1

0

0

0

Input x 7

1

0

1

0

Input x 2

1

0

1

1

Input x 9

1

1

0

0

Input x 8

1

1

0

1

Input x 10

1

1

1

0

Input x 12

1

1

1

1

Input x 16

Name

Number

Type

Description

CLK

1

O

Clock output. Equals the input frequency times selected multiplier.

REFEN

2

I

Reference clock enable. When Low, it disables REFOUT. When High, it

enables REFOUT.

VDD

3,4,5

P

Power Supply.

XOUT

6

O

Crystal output.

S1

7

I

Multiplier Select Pin 1. Determines CLK output. Has internal pull-up.

XIN

8

I

Crystal input to be connected to 10-27MHz fundamental parallel mode crys-

S2

9

I

Multiplier Select Pin 2. Determines CLK output. Has internal pull-up.

S3

10

I

Multiplier Select Pin 3. Determines CLK output. Has internal pull-up.

S0

11

I

Multiplier Select Pin 0. Determines CLK output. Has internal pull-up.

OE

12

I

Output Enable. Tri-state CLK and REFOUT when low. Has internal pull-up.

REFOUT

13

O

Buffered crystal oscillator clock output. Controlled by REFEN.

GND

14,15,16

P

Ground.