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HMC619LP5 数据表(PDF) 18 Page - Analog Devices |
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HMC619LP5 数据表(HTML) 18 Page - Analog Devices |
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18 / 22 page ![]() For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com Application Support: Phone: 978-250-3343 or apps@hittite.com 16 HMC980 v00.0312 Active BiAs controller High current Figure 2. Daisy Chain Operation operation Modes hMC980 can be configured to bias both enhancement and depletion mode external amplifiers. the mode of operation can be selected by setting two pads (VneGFB, VGateFB) as tabulated in table-2. the connection to the VneGin should be adjusted accordingly. in order not to bias external amplifier in a wrong region, please make sure that the correct mode of operation is selected before powering up the hMC980. the hMC980 does not allow the internal negative voltage generator to work if an enhancement mode is selected. therefore, if VneGFB is left floating while VGateFB is grounded, hMC980 will stay in standby mode. please note that in depletion slave mode the external negative voltage should be between -2.3V to -3.5V for hMC980 to operate. if your application requires negative voltages outside this range please contact hittite application support. table 2. Mode selection VneGFB VGateFB VneGin Description MoDe1 (Depletion/Master Mode) Float Float Connected to VneGoUt Depletion mode transistor. internal negative voltage generator is active and generates -2.5V. sample application schematic given shown in Fig.3a. MoDe2 (Depletion/slave Mode) GnD Float Connected to external Vss Depletion mode transistor. internal negative voltage generator is disabled. an external negative voltage less than -2.3V should be connected to VneGin. sample application schematic given shown in Fig.3b. --- Float GnD n/a not allowed. hMC980 stays in standby. MoDe3 (enhancement Mode) GnD GnD Connected to GnD enhancement mode transistor. internal negative voltage generator is disabled. sample application schematic given shown in Fig.3c. |
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