PLL102-03SCL-R datasheet(3/6 Pages) PLL

3 / 6 page

PLL102-03

Low Skew Output Buffer

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 02/23/06 Page 3

3. Switching Characteristics

PARAMETERS

SYMBOL

DESCRIPTION

MIN.

TYP.

MAX.

UNITS

Output Frequency

180

MHz

Duty Cycle ( t2

÷ t1 )

Dt1

Measured at 1.4V, CL=30pF

40.0

50.0

60.0

Duty Cycle ( t2

÷ t1 )

Dt2

Measured at 1.4V

45.0

50.0

55.0

Rise Time

Measured between 0.8V

and 2.0V, CL=30pF

1.2

1.5

Fall Time

Measured between 2.0V

and 0.8V, CL=30pF

1.2

1.5

Output to Output Skew

Tskew

All outputs equally loaded,

CL=20pF

250

Delay, REF Rising Edge to

CLKOUT Rising Edge

Tdelay

Measured at 1.4V

±350

Device to Device Skew

Tdsk-dsk

Measured at VDD/2 on the

CLKOUT pins of devices

700

Cycle to Cycle Jitter

Tcyc-cyc

Measured at 133MHz,

loaded outputs

150

PLL Lock Time

Tlock

Stable power supply, valid

clock presented on REF pin

1.0

Jitter; Absolute Jitter

Tjabs

At 10,000 cycles, CL=30pF

100

Jitter; 1-sigma

Tj1-s

At 10,000 cycles, CL=30pF

SWITCHING WAVEFORMS

Duty Cycle Timing

1.4V

Output - Output Skew

1.4V

SKEW

Output

PLL102-03SCL-R 数据表(PDF) 3 Page - PhaseLink Corporation

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