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PLL601-12SC-R 数据表(PDF) 4 Page - PhaseLink Corporation

部件名 PLL601-12SC-R
功能描述  Dual Output PLL Clock with Selectable Odd Multiplier
PDF  5 Pages
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制造商  PLL [PhaseLink Corporation]
网页  http://www.phaselink.com
标志 PLL - PhaseLink Corporation

PLL601-12SC-R 数据表(HTML) 4 Page - PhaseLink Corporation

  PLL601-12SC-R Datasheet HTML 1Page - PhaseLink Corporation PLL601-12SC-R Datasheet HTML 2Page - PhaseLink Corporation PLL601-12SC-R Datasheet HTML 3Page - PhaseLink Corporation PLL601-12SC-R Datasheet HTML 4Page - PhaseLink Corporation PLL601-12SC-R Datasheet HTML 5Page - PhaseLink Corporation  
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PLL601-12
Dual Output PLL Clock with Selectable Odd Multiplier
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/03/04 Page 4
5. Jitter Specifications
PARAMETERS
CONDITIONS
MIN.
TYP.
MAX.
UNITS
Max. Absolute Jitter, peak-to-peak
Short term
60
100
ps
Max. Jitter, cycle to cycle
60
ps
Phase Noise, relative to carrier, 125Mhz(x5)
100 Hz offset
105
dBc/Hz
Phase Noise, relative to carrier, 125Mhz(x5)
1kHz offset
125
dBc/Hz
Phase Noise, relative to carrier, 125Mhz(x5)
10kHz offset
130
dBc/Hz
Phase Noise, relative to carrier, 125Mhz(x5)
100kHz offset
125
dBc/Hz



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