PLL650-05

Low EMI Network LAN Clock

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/03/04 Page 1

FEATURES

• Full CMOS output swing with 40-mA output drive

capability. 25-mA output drive at TTL level.

• Advanced, low power, sub-micron CMOS processes.

• 25MHz fundamental crystal or clock input.

• 3 fixed outputs of 25MHz, 75Mhz and 125Mhz with

output disable

• SDRAM selectable frequencies of 105, 83.3, 140MHz

(Double Drive Strength).

• Spread spectrum technology selectable for EMI

reduction from

±0.5%, ±0.75% center for SDRAM and

CPU.

• Zero PPM synthesis error in all clocks.

• Ideal for Network switches.

• 3.3V operation.

•

DESCRIPTION

The PLL650-05 is a low cost, low jitter, high

performance clock synthesizer. With PhaseLink’s

proprietary analog Phase Locked Loop techniques, this

device can produce multiple clock outputs from a 25.0MHz

crystal or reference clock. This makes the PLL650-05 an

excellent choice for systems requiring clocking for network

chips, PCI devices, SDRAM, and ASICs.

PIN CONFIGURATION

FREQUENCY TABLE

FS1

FS0

SDRAMX2

0

0

Tristate

0

1

1

0

1

1

BLOCK DIAGRAM

XTAL

OSC

125MHz

(can be disabled)

XIN

XOUT

SDRAM (105, 83.3, 140MHz)

75 MHz

(can be disabled)

Control

Logic

FS (0:1)

1

1

1

25MHz

1

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

VDD

VDD

25MHz/FS0*^

GND

GND

SDRAMx2

VDD

XIN

XOUT/ENB_125M*^

GND

VDD

125MHz

GND

75MHz/FS1*^

ENB_75MHz^

resistor *: Bi-directional pin (input value is latched upon power-up).