EMC2301 datasheet(33/70 Pages) MICROCHIP

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DS20006532A-page 33

EMC2301/2/3/5

6.7

Fan Interrupt Enable Register

The Fan Interrupt Enable register controls the masking

for each fan channel. When a channel is enabled, it will

cause the ALERT pin to be asserted when an Error

condition is detected.

•‘1’ - An Error condition (Stall, Spin Up, Drive Fail)

on fan X will cause the ALERT pin to be asserted.

•‘0’ (default) - An Error condition on fan X will not

cause the ALERT pin to be asserted; however,

the status registers will be updated normally.

FAN INTERRUPT ENABLE - FAN INTERRUPT ENABLE REGISTER (ADDRESS

29H)

U-0

RW-0

—

F5ITEN

F4ITEN

F3ITEN

F2ITEN

F1ITEN

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7-5

Unimplemented bits, read as ‘0’.

bit 4

F5ITEN: Fan 5 Interrupt Enable. Allows Fan 5 to assert the ALERT pin if an error condition is detected

1 = Fan 5 has an Error condition.

0 = Fan 5 is operating within limits.

bit 3

F4ITEN: Fan 4 Interrupt Enable. Allows Fan 4 to assert the ALERT pin if an error condition is detected

1 = Fan 4 has an Error condition.

0 = Fan 4 is operating within limits.

bit 2

F3ITEN: Fan 3 Interrupt Enable. Allows Fan 3 to assert the ALERT pin if an error condition is detected

1 = Fan 3 has an Error condition.

0 = Fan 3 is operating within limits.

bit 1

F2ITEN: Fan 2 Interrupt Enable. Allows Fan 2 to assert the ALERT pin if an error condition is detected

1 = Fan 2 has an Error condition.

0 = Fan 2 is operating within limits.

bit 0

F1ITEN: Fan 1 Interrupt Enable. Allows Fan 1 to assert the ALERT pin if an error condition is detected

1 = Fan 1 has an Error condition.

0 = Fan 1 is operating within limits.

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