Preliminary

PLL600-27B

Ultra Low Current XO 10 MHz to 52 MHz

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/03/05 Page 1

FEATURES

• Low phase noise (-145 dBc @ 10kHz offset).

• CMOS output with OE tri-state control.

• Ultra Low current consumption ( <2mA, at

27MHz, 3.3V)

• 12mA drive capability at TTL output.

• Low jitter (RMS): 2.5ps period jitter.

• 1.8V, 2.5V and 3.3V DC operation.

• Available in 8 pin SOIC

DESCRIPTION

The PLL600-27B form a low cost family of XO IC’s,

designed to consume the lowest current on the mar-

ket for the 10MHz to 52MHz range. It accepts fun-

damental resonant mode crystal input from 10 to

52MHz. Providing less than -145 dBc at 10kHz offset

at 30MHz and with a very low jitter (2.5 ps RMS pe-

riod jitter) makes this chip ideal for applications re-

quiring low current frequency sources.

BLOCK DIAGRAM

PIN ASSIGNMENT (PACKAGE)

8-pin SOIC

PAD LAYOUT

OE LOGIC SELECTION TABLE

OE^

OUTPUT

0

Disabled - osc. off

1(default)

Enabled

SOT-23

1

2

3

4

5

6

GND

CLK

XOUT

XIN/FIN

OE^

VDD

XTAL

OSC

XIN/FIN

XOUT

CLK

OE

OSCSEL

1

2

3

4

XIN/FIN

5

6

7

8

OE^

DNC

GND

XOUT

DNC

VDD

CLK

^ : denotes internal pull-up

Y

X

(0,0)

32 mil

Die ID:

1

2

3

4

5

6

7

8

XOUT

DNC

VDD

CLK

XIN

OE

DNC

GND

(812, 986)