PCF8536AT datasheet(8/51 Pages) NXP

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NXP Semiconductors

PCF8551

Universal 36 × 4 LCD segment driver

Bit

Symbol

Value

Description

7 to 4

0000

default value

frame frequency selection

ffr = 32 Hz

01[1]

ffr = 64 Hz

ffr = 96 Hz

3 to 2

FF[1:0]

ffr = 128 Hz

internal oscillator control

0[1]

enabled

OSC

disabled

clock output enable

0[1]

clock signal not available on pin CLK;

pin CLK is in 3-state

COE

clock signal available on pin CLK

Table 5. Device_ctrl - device control command register (address 01h) bit

description

[1]

Default value.

7.2.1.1 Internal oscillator and clock output

Bit OSC enables or disables the internal oscillator. When the internal oscillator is used,

bit COE allows making the clock signal available on pin CLK. If this is not intended, pin

CLK should be left open. The design ensures that the duty cycle of the clock output is

50 : 50 (% HIGH-level time : % LOW-level time).

In power-down mode (see Section 7.3.1)

• if pin CLK is configured as an output, there is no signal on CLK

• if pin CLK is configured as an input, the signal on CLK can be removed.

In applications where an external clock has to be applied to the PCF8551, bit OSC must

be set logic 1 and COE logic 0. In this case pin CLK becomes an input.

Remark: A clock signal must always be supplied to the device if the display is enabled

(see bit DE in Table 6). Removing the clock may freeze the LCD in a DC state, which is

not suitable for the liquid crystal.

7.2.2 Command: Display_ctrl_1

The Display_ctrl_1 command allows configuring the basic display set-up.

Bit

Symbol

Value

Description

7 to 5

000

default value

large display mode support

BOOST

0[1]

standard power drive scheme

Table 6. Display_ctrl_1 - display control command 1 register (address 02h) bit

description

PCF8551

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3.1 — 3 May 2021

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