Preliminary

PLL701-21

Low EMI Spread Spectrum Multiplier Clock

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991

www.phaselink.com

Rev 05/12/05 Page 2

BLOCK DIAGRAM

PIN DESCRIPTIONS

Name

Number

Type

Description

FIN

1

I

Input Clock Frequency. 24MHz to 200MHz.

S2

2

I

Digital control input for SST modulation magnitude selection. Has internal pull-

up.

S1

3

I

Digital control input for SST modulation magnitude selection. Has internal pull-

up.

S0

4

I

Digital control input for SST modulation magnitude selection. Has internal pull-

down.

GND

5

P

Ground.

FOUT

6

O

SST Modulated Clock Frequency Output.

S3

7

I

SST By-Pass Selector. S3 has internal pull-up. Default =”1”

VDD

8

P

3.3V Power Supply.

ELECTRICAL SPECIFICATIONS

1. Absolute Maximum Ratings

PARAMETERS

SYMBOL

MIN.

MAX.

UNITS

Supply Voltage

4.6

V

Input Voltage, dc

-0.5

V

Output Voltage, dc

-0.5

V

Storage Temperature

-65

150

°C

Ambient Operating Temperature*

-40

85

°C

Junction Temperature

125

°C

Lead Temperature (soldering, 10s)

260

°C

ESD Protection, Human Body Model

2

kV

Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the

device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other

conditions above the operational limits noted in this specification is not implied.

* Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only.

FOUT

FIN

S(0:3)

PLL

SST

Control

Logic