Preliminary

PLL701-21

Low EMI Spread Spectrum Multiplier Clock

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991

www.phaselink.com

Rev 05/12/05 Page 3

2. DC/AC Specifications

PARAMETERS

SYMBOL

CONDITIONS

MIN.

TYP.

MAX.

UNITS

Supply Voltage

2.97

3.63

V

Input High Voltage

V

Input Low Voltage

V

Input High Current

100

µA

Input Low Current

100

µA

Output High Voltage

2.4

V

Output Low Voltage

0.4

V

Input Frequency

24

200

MHz

100

µs

Input Capacitance

4

pF

Pull-up Resistor

PIN 2, 3, 7

30

k

Ω

Pull-down Resistor

PIN 4

30

k

Ω

Short Circuit Current

50

mA

3.3V Dynamic Supply Current

No Load

20

mA

3. TIMING CHARACTERISTICS

PARAMETERS

SYMBOL

CONDITIONS

MIN.

TYP.

MAX.

UNITS

Rise Time

Measured at 0.8V ~ 2.0V @ 3.3V

0.8

0.95

1.1

ns

Fall Time

Measured at 2.0V ~ 0.8V @ 3.3V

0.78

0.85

0.9

ns

Output Duty Cycle

45

50

55

%

Input to Output Delay

2

4

ns

Cycle to Cycle Jitter

Over output frequency range @ 3.3V

100

ps

FUNCTIONAL DESCRIPTION

Selectable spread spectrum and modulation rates

The PLL701-21 provides Center Spread modulation, as well as a selectable modulation magnitude. Selection is

made by connecting pins 2 (S2), 3 (S1) and 4 (S0) to a logical “zero” or “one”, according to the modulation

magnitude selection table on page 1.

Default values for S(0:3) through internal pull-up and pull-down resistor

Selection pin 4 (S0) has an internal pull-down resistor of 30k

Ω while pins 2, 3 and 7 (S2, S1 and S3) have an

internal pull-up resistor of 30k

Ω. This internal pull-down (or pull-up) resistor will pull the input value to a logical

“zero” (or “one” respectively) by default, i.e. when no connection is made between the pin and VDD (GND

respectively). In order to override the internal pull-down (pull-up), the pin has to be connected to VDD (GND

respectively).